4  *  Copyright (C) 2001-2002  MontaVista Software Inc.
6  *  Copyright (C) 2003-2006  Yoichi Yuasa <yuasa@linux-mips.org>
20  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
25  *  - New creation, NEC VR4122 and VR4131 are supported.
26  *  - Added support for NEC VR4111 and VR4121.
28  *  Yoichi Yuasa <yuasa@linux-mips.org>
29  *  - Coped with INTASSIGN of NEC VR4133.
97 #define SYSINT1_IRQ_TO_PIN(x)	((x) - SYSINT1_IRQ_BASE)	/* Pin 0-15 */
98 #define SYSINT2_IRQ_TO_PIN(x)	((x) - SYSINT2_IRQ_BASE)	/* Pin 0-15 */
100 #define INT_TO_IRQ(x)		((x) + 2)	/* Int0-4 -> IRQ2-6 */
102 #define icu1_read(offset)		readw(icu1_base + (offset))  argument
103 #define icu1_write(offset, value)	writew((value), icu1_base + (offset))  argument
105 #define icu2_read(offset)		readw(icu2_base + (offset))  argument
106 #define icu2_write(offset, value)	writew((value), icu2_base + (offset))  argument
111 static inline uint16_t icu1_set(uint8_t offset, uint16_t set)  in icu1_set()  argument
115 	data = icu1_read(offset);  in icu1_set()
117 	icu1_write(offset, data);  in icu1_set()
122 static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear)  in icu1_clear()  argument
126 	data = icu1_read(offset);  in icu1_clear()
128 	icu1_write(offset, data);  in icu1_clear()
133 static inline uint16_t icu2_set(uint8_t offset, uint16_t set)  in icu2_set()  argument
137 	data = icu2_read(offset);  in icu2_set()
139 	icu2_write(offset, data);  in icu2_set()
144 static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear)  in icu2_clear()  argument
148 	data = icu2_read(offset);  in icu2_clear()
150 	icu2_write(offset, data);  in icu2_clear()
162 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_piuint()
164 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_piuint()
177 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_piuint()
179 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_piuint()
192 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_aiuint()
194 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_aiuint()
207 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_aiuint()
209 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_aiuint()
222 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_kiuint()
224 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_kiuint()
237 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_kiuint()
239 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_kiuint()
250 	raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_macint()
252 	raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_macint()
262 	raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_macint()
264 	raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_macint()
274 	raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_dsiuint()
276 	raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_dsiuint()
286 	raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_dsiuint()
288 	raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_dsiuint()
298 	raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_firint()
300 	raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_firint()
310 	raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_firint()
312 	raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_firint()
325 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_pciint()
327 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_pciint()
341 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_pciint()
343 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_pciint()
357 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_scuint()
359 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_scuint()
373 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_scuint()
375 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_scuint()
389 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_csiint()
391 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_csiint()
405 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_csiint()
407 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_csiint()
421 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_enable_bcuint()
423 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_enable_bcuint()
437 		raw_spin_lock_irqsave(&desc->lock, flags);  in vr41xx_disable_bcuint()
439 		raw_spin_unlock_irqrestore(&desc->lock, flags);  in vr41xx_disable_bcuint()
447 	icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq));  in disable_sysint1_irq()
452 	icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq));  in enable_sysint1_irq()
463 	icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq));  in disable_sysint2_irq()
468 	icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq));  in enable_sysint2_irq()
485 	raw_spin_lock_irq(&desc->lock);  in set_sysint1_assign()
524 		raw_spin_unlock_irq(&desc->lock);  in set_sysint1_assign()
525 		return -EINVAL;  in set_sysint1_assign()
532 	raw_spin_unlock_irq(&desc->lock);  in set_sysint1_assign()
545 	raw_spin_lock_irq(&desc->lock);  in set_sysint2_assign()
592 		raw_spin_unlock_irq(&desc->lock);  in set_sysint2_assign()
593 		return -EINVAL;  in set_sysint2_assign()
600 	raw_spin_unlock_irq(&desc->lock);  in set_sysint2_assign()
607 	int retval = -EINVAL;  in vr41xx_set_intassign()
610 		return -EINVAL;  in vr41xx_set_intassign()
613 		return -EINVAL;  in vr41xx_set_intassign()
658 	return -1;  in icu_get_irq()
680 		return -ENODEV;  in vr41xx_icu_init()
684 		return -EBUSY;  in vr41xx_icu_init()
688 		return -EBUSY;  in vr41xx_icu_init()
695 		return -ENOMEM;  in vr41xx_icu_init()
703 		return -ENOMEM;  in vr41xx_icu_init()