Lines Matching full:definitions

4  * SPR Definitions
138  * Bit definitions for the Version Register
152  * Bit definitions for the Version Register 2
158  * Bit definitions for the Unit Present Register
176  * JPB: Bit definitions for the CPU configuration register
189  * JPB: Bit definitions for the Debug configuration register and other
216  * Bit definitions for the Supervision Register
240  * Bit definitions for the Data MMU Control Register
249  * Bit definitions for the Instruction MMU Control Register
258  * Bit definitions for the Data TLB Match Register
268  * Bit definitions for the Data TLB Translate Register
284  * Bit definitions for the Instruction TLB Match Register
294  * Bit definitions for the Instruction TLB Translate Register
308  * Bit definitions for Data Cache Control register
314  * Bit definitions for Insn Cache Control register
320  * Bit definitions for Data Cache Configuration Register
340  * Bit definitions for Instruction Cache Configuration Register
356  * Bit definitions for Data MMU Configuration Register
372  * Bit definitions for Instruction MMU Configuration Register
388  * Bit definitions for Debug Control registers
417  * Bit definitions for Debug Mode 1 register
457  * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
470  * Bit definitions for Debug watchpoint counter registers
478  * Bit definitions for Debug stop register
497  * Bit definitions for Debug reason register
516  * Bit definitions for Performance counters mode registers
537  * Bit definitions for the Power management register
547  * Bit definitions for PICMR
553  * Bit definitions for PICPR
559  * Bit definitions for PICSR
565  * Bit definitions for Tick Timer Control Register
580  * Bit definitions for the FP Control Status Register