Lines Matching +full:u +full:- +full:boot
28 * MA 02111-1307 USA
31 /dts-v1/;
34 #address-cells = <2>;
35 #size-cells = <1>;
38 dcr-parent = <&{/cpus/cpu@0}>;
48 #address-cells = <1>;
49 #size-cells = <0>;
55 clock-frequency = <0>; /* Filled in by U-Boot */
56 timebase-frequency = <0>; /* Filled in by U-Boot */
57 i-cache-line-size = <32>;
58 d-cache-line-size = <32>;
59 i-cache-size = <32768>;
60 d-cache-size = <32768>;
61 dcr-controller;
62 dcr-access-method = "native";
63 next-level-cache = <&L2C0>;
69 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
72 UIC0: interrupt-controller0 {
73 compatible = "ibm,uic-460gt","ibm,uic";
74 interrupt-controller;
75 cell-index = <0>;
76 dcr-reg = <0x0c0 0x009>;
77 #address-cells = <0>;
78 #size-cells = <0>;
79 #interrupt-cells = <2>;
82 UIC1: interrupt-controller1 {
83 compatible = "ibm,uic-460gt","ibm,uic";
84 interrupt-controller;
85 cell-index = <1>;
86 dcr-reg = <0x0d0 0x009>;
87 #address-cells = <0>;
88 #size-cells = <0>;
89 #interrupt-cells = <2>;
91 interrupt-parent = <&UIC0>;
94 UIC2: interrupt-controller2 {
95 compatible = "ibm,uic-460gt","ibm,uic";
96 interrupt-controller;
97 cell-index = <2>;
98 dcr-reg = <0x0e0 0x009>;
99 #address-cells = <0>;
100 #size-cells = <0>;
101 #interrupt-cells = <2>;
103 interrupt-parent = <&UIC0>;
106 UIC3: interrupt-controller3 {
107 compatible = "ibm,uic-460gt","ibm,uic";
108 interrupt-controller;
109 cell-index = <3>;
110 dcr-reg = <0x0f0 0x009>;
111 #address-cells = <0>;
112 #size-cells = <0>;
113 #interrupt-cells = <2>;
115 interrupt-parent = <&UIC0>;
119 compatible = "ibm,sdr-460gt";
120 dcr-reg = <0x00e 0x002>;
124 compatible = "ibm,cpr-460gt";
125 dcr-reg = <0x00c 0x002>;
129 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
130 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
132 cache-line-size = <32>; /* 32 bytes */
133 cache-size = <262144>; /* L2, 256K */
134 interrupt-parent = <&UIC1>;
139 compatible = "ibm,plb-460gt", "ibm,plb4";
140 #address-cells = <2>;
141 #size-cells = <1>;
143 clock-frequency = <0>; /* Filled in by U-Boot */
146 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
147 dcr-reg = <0x010 0x002>;
151 compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
153 interrupt-parent = <&UIC0>;
158 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
159 dcr-reg = <0x180 0x062>;
160 num-tx-chans = <3>;
161 num-rx-chans = <24>;
162 #address-cells = <0>;
163 #size-cells = <0>;
164 interrupt-parent = <&UIC2>;
170 desc-base-addr-high = <0x8>;
174 compatible = "ibm,opb-460gt", "ibm,opb";
175 #address-cells = <1>;
176 #size-cells = <1>;
178 clock-frequency = <0>; /* Filled in by U-Boot */
181 compatible = "ibm,ebc-460gt", "ibm,ebc";
182 dcr-reg = <0x012 0x002>;
183 #address-cells = <2>;
184 #size-cells = <1>;
185 clock-frequency = <0>; /* Filled in by U-Boot */
186 /* ranges property is supplied by U-Boot */
188 interrupt-parent = <&UIC1>;
191 compatible = "amd,s29gl256n", "cfi-flash";
192 bank-width = <2>;
194 #address-cells = <1>;
195 #size-cells = <1>;
217 label = "u-boot";
227 virtual-reg = <0xef600300>;
228 clock-frequency = <0>; /* Filled in by U-Boot */
229 current-speed = <0>; /* Filled in by U-Boot */
230 interrupt-parent = <&UIC1>;
235 compatible = "ibm,iic-460gt", "ibm,iic";
237 interrupt-parent = <&UIC0>;
239 #address-cells = <1>;
240 #size-cells = <0>;
244 interrupt-parent = <&UIC1>;
250 compatible = "ibm,iic-460gt", "ibm,iic";
252 interrupt-parent = <&UIC0>;
256 TAH0: emac-tah@ef601350 {
257 compatible = "ibm,tah-460gt", "ibm,tah";
261 TAH1: emac-tah@ef601450 {
262 compatible = "ibm,tah-460gt", "ibm,tah";
268 compatible = "ibm,emac-460gt", "ibm,emac4sync";
269 interrupt-parent = <&EMAC0>;
271 #interrupt-cells = <1>;
272 #address-cells = <0>;
273 #size-cells = <0>;
274 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
277 local-mac-address = [000000000000]; /* Filled in by U-Boot */
278 mal-device = <&MAL0>;
279 mal-tx-channel = <0>;
280 mal-rx-channel = <0>;
281 cell-index = <0>;
282 max-frame-size = <9000>;
283 rx-fifo-size = <4096>;
284 tx-fifo-size = <2048>;
285 rx-fifo-size-gige = <16384>;
286 phy-mode = "sgmii";
287 phy-map = <0xffffffff>;
288 gpcs-address = <0x0000000a>;
289 tah-device = <&TAH0>;
290 tah-channel = <0>;
291 has-inverted-stacr-oc;
292 has-new-stacr-staopc;
297 compatible = "ibm,emac-460gt", "ibm,emac4sync";
298 interrupt-parent = <&EMAC1>;
300 #interrupt-cells = <1>;
301 #address-cells = <0>;
302 #size-cells = <0>;
303 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
306 local-mac-address = [000000000000]; /* Filled in by U-Boot */
307 mal-device = <&MAL0>;
308 mal-tx-channel = <1>;
309 mal-rx-channel = <8>;
310 cell-index = <1>;
311 max-frame-size = <9000>;
312 rx-fifo-size = <4096>;
313 tx-fifo-size = <2048>;
314 rx-fifo-size-gige = <16384>;
315 phy-mode = "sgmii";
316 phy-map = <0x00000000>;
317 gpcs-address = <0x0000000b>;
318 tah-device = <&TAH1>;
319 tah-channel = <1>;
320 has-inverted-stacr-oc;
321 has-new-stacr-staopc;
322 mdio-device = <&EMAC0>;
327 compatible = "ibm,emac-460gt", "ibm,emac4sync";
328 interrupt-parent = <&EMAC2>;
330 #interrupt-cells = <1>;
331 #address-cells = <0>;
332 #size-cells = <0>;
333 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
336 local-mac-address = [000000000000]; /* Filled in by U-Boot */
337 mal-device = <&MAL0>;
338 mal-tx-channel = <2>;
339 mal-rx-channel = <16>;
340 cell-index = <2>;
341 max-frame-size = <9000>;
342 rx-fifo-size = <4096>;
343 tx-fifo-size = <2048>;
344 rx-fifo-size-gige = <16384>;
345 tx-fifo-size-gige = <16384>; /* emac2&3 only */
346 phy-mode = "sgmii";
347 phy-map = <0x00000001>;
348 gpcs-address = <0x0000000C>;
349 has-inverted-stacr-oc;
350 has-new-stacr-staopc;
351 mdio-device = <&EMAC0>;