Lines Matching +full:u +full:- +full:boot
20 * MA 02111-1307 USA
24 /dts-v1/;
27 #address-cells = <2>;
28 #size-cells = <1>;
31 dcr-parent = <&{/cpus/cpu@0}>;
40 #address-cells = <1>;
41 #size-cells = <0>;
47 clock-frequency = <0>; /* Filled in by U-Boot */
48 timebase-frequency = <0>; /* Filled in by U-Boot */
49 i-cache-line-size = <32>;
50 d-cache-line-size = <32>;
51 i-cache-size = <32768>;
52 d-cache-size = <32768>;
53 dcr-controller;
54 dcr-access-method = "native";
55 next-level-cache = <&L2C0>;
61 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
64 UIC0: interrupt-controller0 {
66 interrupt-controller;
67 cell-index = <0>;
68 dcr-reg = <0x0c0 0x009>;
69 #address-cells = <0>;
70 #size-cells = <0>;
71 #interrupt-cells = <2>;
74 UIC1: interrupt-controller1 {
76 interrupt-controller;
77 cell-index = <1>;
78 dcr-reg = <0x0d0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
83 interrupt-parent = <&UIC0>;
86 UIC2: interrupt-controller2 {
88 interrupt-controller;
89 cell-index = <2>;
90 dcr-reg = <0x0e0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
95 interrupt-parent = <&UIC0>;
98 UIC3: interrupt-controller3 {
100 interrupt-controller;
101 cell-index = <3>;
102 dcr-reg = <0x0f0 0x009>;
103 #address-cells = <0>;
104 #size-cells = <0>;
105 #interrupt-cells = <2>;
107 interrupt-parent = <&UIC0>;
113 cell-index = <1>;
114 /* configured in U-Boot */
119 compatible = "ibm,sdr-apm821xx";
120 dcr-reg = <0x00e 0x002>;
124 compatible = "ibm,cpr-apm821xx";
125 dcr-reg = <0x00c 0x002>;
129 compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
130 dcr-reg = <0x020 0x008
132 cache-line-size = <32>;
133 cache-size = <262144>;
134 interrupt-parent = <&UIC1>;
140 #address-cells = <2>;
141 #size-cells = <1>;
143 clock-frequency = <0>; /* Filled in by U-Boot */
146 compatible = "ibm,sdram-apm821xx";
147 dcr-reg = <0x010 0x002>;
152 descriptor-memory = "ocm";
153 dcr-reg = <0x180 0x062>;
154 num-tx-chans = <1>;
155 num-rx-chans = <1>;
156 #address-cells = <0>;
157 #size-cells = <0>;
158 interrupt-parent = <&UIC2>;
168 #address-cells = <1>;
169 #size-cells = <1>;
171 clock-frequency = <0>; /* Filled in by U-Boot */
175 dcr-reg = <0x012 0x002>;
176 #address-cells = <2>;
177 #size-cells = <1>;
178 clock-frequency = <0>; /* Filled in by U-Boot */
179 /* ranges property is supplied by U-Boot */
182 interrupt-parent = <&UIC1>;
185 compatible = "amd,s29gl512n", "cfi-flash";
186 bank-width = <2>;
188 #address-cells = <1>;
189 #size-cells = <1>;
199 label = "u-boot";
208 bank-settings = <0x80002222>;
209 #address-cells = <1>;
210 #size-cells = <1>;
213 #address-cells = <1>;
214 #size-cells = <1>;
233 label = "device-tree";
256 virtual-reg = <0xef600300>;
257 clock-frequency = <0>; /* Filled in by U-Boot */
258 current-speed = <0>; /* Filled in by U-Boot */
259 interrupt-parent = <&UIC1>;
267 virtual-reg = <0xef600400>;
268 clock-frequency = <0>; /* Filled in by U-Boot */
269 current-speed = <0>; /* Filled in by U-Boot */
270 interrupt-parent = <&UIC0>;
277 interrupt-parent = <&UIC0>;
279 #address-cells = <1>;
280 #size-cells = <0>;
284 interrupt-parent = <&UIC0>;
290 interrupt-parent = <&UIC1>;
298 interrupt-parent = <&UIC0>;
302 RGMII0: emac-rgmii@ef601500 {
305 has-mdio;
308 TAH0: emac-tah@ef601350 {
315 compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
316 interrupt-parent = <&EMAC0>;
318 #interrupt-cells = <1>;
319 #address-cells = <0>;
320 #size-cells = <0>;
321 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
324 local-mac-address = [000000000000]; /* Filled in by U-Boot */
325 mal-device = <&MAL0>;
326 mal-tx-channel = <0>;
327 mal-rx-channel = <0>;
328 cell-index = <0>;
329 max-frame-size = <9000>;
330 rx-fifo-size = <16384>;
331 tx-fifo-size = <2048>;
332 phy-mode = "rgmii";
333 phy-map = <0x00000000>;
334 rgmii-device = <&RGMII0>;
335 rgmii-channel = <0>;
336 tah-device = <&TAH0>;
337 tah-channel = <0>;
338 has-inverted-stacr-oc;
339 has-new-stacr-staopc;
345 #interrupt-cells = <1>;
346 #size-cells = <2>;
347 #address-cells = <3>;
348 compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
353 dcr-reg = <0x100 0x020>;
354 sdr-base = <0x300>;
364 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
367 bus-range = <0x40 0x7f>;
371 * We are de-swizzling here because the numbers are actually for
374 * below are basically de-swizzled numbers.
377 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
378 interrupt-map = <
385 MSI: ppc4xx-msi@C10000000 {
386 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
389 sdr-base = <0x36C>;
390 msi-data = <0x00004440>;
391 msi-mask = <0x0000ffe0>;
393 interrupt-parent = <&MSI>;
394 #interrupt-cells = <1>;
395 #address-cells = <0>;
396 #size-cells = <0>;
397 msi-available-ranges = <0x0 0x100>;
398 interrupt-map = <