Lines Matching +full:0 +full:x00000060
35 #define BR_BA 0xFFFF8000
37 #define BR_PS 0x00001800
39 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
40 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
41 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
42 #define BR_DECC 0x00000600
44 #define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
45 #define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
46 #define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
47 #define BR_WP 0x00000100
49 #define BR_MSEL 0x000000E0
51 #define BR_MS_GPCM 0x00000000 /* GPCM */
52 #define BR_MS_FCM 0x00000020 /* FCM */
53 #define BR_MS_SDRAM 0x00000060 /* SDRAM */
54 #define BR_MS_UPMA 0x00000080 /* UPMA */
55 #define BR_MS_UPMB 0x000000A0 /* UPMB */
56 #define BR_MS_UPMC 0x000000C0 /* UPMC */
57 #define BR_V 0x00000001
58 #define BR_V_SHIFT 0
62 #define OR0 0x5004
63 #define OR1 0x500C
64 #define OR2 0x5014
65 #define OR3 0x501C
66 #define OR4 0x5024
67 #define OR5 0x502C
68 #define OR6 0x5034
69 #define OR7 0x503C
71 #define OR_FCM_AM 0xFFFF8000
73 #define OR_FCM_BCTLD 0x00001000
75 #define OR_FCM_PGS 0x00000400
77 #define OR_FCM_CSCT 0x00000200
79 #define OR_FCM_CST 0x00000100
81 #define OR_FCM_CHT 0x00000080
83 #define OR_FCM_SCY 0x00000070
85 #define OR_FCM_SCY_1 0x00000010
86 #define OR_FCM_SCY_2 0x00000020
87 #define OR_FCM_SCY_3 0x00000030
88 #define OR_FCM_SCY_4 0x00000040
89 #define OR_FCM_SCY_5 0x00000050
90 #define OR_FCM_SCY_6 0x00000060
91 #define OR_FCM_SCY_7 0x00000070
92 #define OR_FCM_RST 0x00000008
94 #define OR_FCM_TRLX 0x00000004
96 #define OR_FCM_EHTR 0x00000002
99 #define OR_GPCM_AM 0xFFFF8000
105 u8 res0[0x8];
107 u8 res1[0x4];
109 #define MxMR_OP_NO (0 << 28) /**< normal operation */
113 #define MxMR_MAD 0x3f /**< machine address */
116 u8 res2[0x8];
119 u8 res3[0x4];
122 u8 res4[0x8];
125 u8 res5[0x8];
127 #define LTESR_BM 0x80000000
128 #define LTESR_FCT 0x40000000
129 #define LTESR_PAR 0x20000000
130 #define LTESR_WP 0x04000000
131 #define LTESR_ATMW 0x00800000
132 #define LTESR_ATMR 0x00400000
133 #define LTESR_CS 0x00080000
134 #define LTESR_UPM 0x00000002
135 #define LTESR_CC 0x00000001
140 #define LTESR_CLEAR 0xFFFFFFFF
141 #define LTECCR_CLEAR 0xFFFFFFFF
144 #define LTEDR_ENABLE 0x00000000
150 u8 res6[0x8];
152 #define LBCR_LDIS 0x80000000
154 #define LBCR_BCTLC 0x00C00000
156 #define LBCR_AHD 0x00200000
157 #define LBCR_LPBSE 0x00020000
159 #define LBCR_EPAR 0x00010000
161 #define LBCR_BMT 0x0000FF00
163 #define LBCR_BMTPS 0x0000000F
164 #define LBCR_BMTPS_SHIFT 0
165 #define LBCR_INIT 0x00040000
167 #define LCRR_DBYP 0x80000000
169 #define LCRR_BUFCMDC 0x30000000
171 #define LCRR_ECL 0x03000000
173 #define LCRR_EADC 0x00030000
175 #define LCRR_CLKDIV 0x0000000F
176 #define LCRR_CLKDIV_SHIFT 0
177 u8 res7[0x8];
179 #define FMR_CWTO 0x0000F000
181 #define FMR_BOOT 0x00000800
182 #define FMR_ECCM 0x00000100
183 #define FMR_AL 0x00000030
185 #define FMR_OP 0x00000003
186 #define FMR_OP_SHIFT 0
188 #define FIR_OP0 0xF0000000
190 #define FIR_OP1 0x0F000000
192 #define FIR_OP2 0x00F00000
194 #define FIR_OP3 0x000F0000
196 #define FIR_OP4 0x0000F000
198 #define FIR_OP5 0x00000F00
200 #define FIR_OP6 0x000000F0
202 #define FIR_OP7 0x0000000F
203 #define FIR_OP7_SHIFT 0
204 #define FIR_OP_NOP 0x0 /* No operation and end of sequence */
205 #define FIR_OP_CA 0x1 /* Issue current column address */
206 #define FIR_OP_PA 0x2 /* Issue current block+page address */
207 #define FIR_OP_UA 0x3 /* Issue user defined address */
208 #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
209 #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
210 #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
211 #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
212 #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
213 #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
214 #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
215 #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
216 #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
217 #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
218 #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
219 #define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
221 #define FCR_CMD0 0xFF000000
223 #define FCR_CMD1 0x00FF0000
225 #define FCR_CMD2 0x0000FF00
227 #define FCR_CMD3 0x000000FF
228 #define FCR_CMD3_SHIFT 0
230 #define FBAR_BLK 0x00FFFFFF
232 #define FPAR_SP_PI 0x00007C00
234 #define FPAR_SP_MS 0x00000200
235 #define FPAR_SP_CI 0x000001FF
236 #define FPAR_SP_CI_SHIFT 0
237 #define FPAR_LP_PI 0x0003F000
239 #define FPAR_LP_MS 0x00000800
240 #define FPAR_LP_CI 0x000007FF
241 #define FPAR_LP_CI_SHIFT 0
243 #define FBCR_BC 0x00000FFF