Lines Matching full:compare
73 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
74 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
75 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
76 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
173 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
202 #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
203 #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
204 #define SPRN_DAC1 0x13C /* Data Address Compare 1 */
205 #define SPRN_DAC2 0x13D /* Data Address Compare 2 */
219 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
220 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
325 #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
326 #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
327 #define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
328 #define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
329 #define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
330 #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
331 #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
332 #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
336 #define DBSR_IAC12ATS 0x00000002 /* Instr Address Compare 1/2 Toggle */
337 #define DBSR_IAC34ATS 0x00000001 /* Instr Address Compare 3/4 Toggle */
344 #define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */
345 #define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */
346 #define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */
347 #define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */
348 #define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */
349 #define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */
350 #define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */
351 #define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */
389 #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
391 #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
395 #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
397 #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
452 #define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */
453 #define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */
454 #define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */
455 #define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */
702 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
703 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
704 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
705 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
706 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
711 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
712 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
713 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */