Lines Matching +full:0 +full:x10a0
45 #define VID 0x03 /* MPIC version ID */
48 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
49 #define OPENPIC_FLAG_ILR (2 << 0)
52 #define OPENPIC_REG_SIZE 0x40000
53 #define OPENPIC_GLB_REG_START 0x0
54 #define OPENPIC_GLB_REG_SIZE 0x10F0
55 #define OPENPIC_TMR_REG_START 0x10F0
56 #define OPENPIC_TMR_REG_SIZE 0x220
57 #define OPENPIC_MSI_REG_START 0x1600
58 #define OPENPIC_MSI_REG_SIZE 0x200
59 #define OPENPIC_SUMMARY_REG_START 0x3800
60 #define OPENPIC_SUMMARY_REG_SIZE 0x800
61 #define OPENPIC_SRC_REG_START 0x10000
62 #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
63 #define OPENPIC_CPU_REG_START 0x20000
64 #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
80 #define FRR_VID_SHIFT 0
85 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
87 #define GCR_RESET 0x80000000
88 #define GCR_MODE_PASS 0x00000000
89 #define GCR_MODE_MIXED 0x20000000
90 #define GCR_MODE_PROXY 0x60000000
92 #define TBCR_CI 0x80000000 /* count inhibit */
93 #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
100 #define IDR_P0_SHIFT 0
102 #define ILR_INTTGT_MASK 0x000000ff
103 #define ILR_INTTGT_INT 0x00
104 #define ILR_INTTGT_CINT 0x01 /* critical */
105 #define ILR_INTTGT_MCP 0x02 /* machine check */
108 #define MSIIR_OFFSET 0x140
110 #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
112 #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
133 IRQ_TYPE_NORMAL = 0,
170 #define IVPR_PRIORITY_MASK (0xF << 16)
174 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
175 #define IDR_EP 0x80000000 /* external pin */
176 #define IDR_CI 0x40000000 /* critical interrupt */
251 __func__, (int)(dst - &opp->dst[0])); in mpic_irq_raise()
269 __func__, (int)(dst - &opp->dst[0])); in mpic_irq_lower()
348 dst->outputs_active[src->output]++ == 0) { in IRQ_local_pipe()
355 --dst->outputs_active[src->output] == 0) { in IRQ_local_pipe()
380 active = 0; in IRQ_local_pipe()
384 if (IRQ_get_next(opp, &dst->servicing) >= 0 && in IRQ_local_pipe()
443 if (src->destmask == 0) { in openpic_update_irq()
454 for (i = 0; i < opp->nb_cpus; i++) { in openpic_update_irq()
464 i = 0; in openpic_update_irq()
487 pr_debug("openpic: set irq %d = %d ivpr=0x%08x\n", in openpic_set_irq()
507 src->pending = 0; in openpic_set_irq()
522 opp->pir = 0; in openpic_reset()
526 for (i = 0; i < opp->max_irq; i++) { in openpic_reset()
546 for (i = 0; i < MAX_CPU; i++) { in openpic_reset()
548 memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue)); in openpic_reset()
550 memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue)); in openpic_reset()
554 for (i = 0; i < MAX_TMR; i++) { in openpic_reset()
555 opp->timers[i].tccr = 0; in openpic_reset()
559 opp->gcr = 0; in openpic_reset()
572 return 0xffffffff; in read_IRQreg_ilr()
585 uint32_t crit_mask = 0; in write_IRQreg_idr()
596 pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); in write_IRQreg_idr()
607 src->destmask = 0; in write_IRQreg_idr()
609 for (i = 0; i < opp->nb_cpus; i++) { in write_IRQreg_idr()
632 pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, in write_IRQreg_ilr()
635 /* TODO: on MPIC v4.0 only, set nomask for non-INT */ in write_IRQreg_ilr()
644 /* NOTE when implementing newer FSL MPIC models: starting with v4.0, in write_IRQreg_ivpr()
674 pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, in write_IRQreg_ivpr()
692 int err = 0; in openpic_gbl_write()
695 if (addr & 0xF) in openpic_gbl_write()
696 return 0; in openpic_gbl_write()
699 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ in openpic_gbl_write()
701 case 0x40: in openpic_gbl_write()
702 case 0x50: in openpic_gbl_write()
703 case 0x60: in openpic_gbl_write()
704 case 0x70: in openpic_gbl_write()
705 case 0x80: in openpic_gbl_write()
706 case 0x90: in openpic_gbl_write()
707 case 0xA0: in openpic_gbl_write()
708 case 0xB0: in openpic_gbl_write()
712 case 0x1000: /* FRR */ in openpic_gbl_write()
714 case 0x1020: /* GCR */ in openpic_gbl_write()
717 case 0x1080: /* VIR */ in openpic_gbl_write()
719 case 0x1090: /* PIR */ in openpic_gbl_write()
726 case 0x10A0: /* IPI_IVPR */ in openpic_gbl_write()
727 case 0x10B0: in openpic_gbl_write()
728 case 0x10C0: in openpic_gbl_write()
729 case 0x10D0: { in openpic_gbl_write()
731 idx = (addr - 0x10A0) >> 4; in openpic_gbl_write()
735 case 0x10E0: /* SPVE */ in openpic_gbl_write()
749 int err = 0; in openpic_gbl_read()
752 retval = 0xFFFFFFFF; in openpic_gbl_read()
753 if (addr & 0xF) in openpic_gbl_read()
757 case 0x1000: /* FRR */ in openpic_gbl_read()
761 case 0x1020: /* GCR */ in openpic_gbl_read()
764 case 0x1080: /* VIR */ in openpic_gbl_read()
767 case 0x1090: /* PIR */ in openpic_gbl_read()
768 retval = 0x00000000; in openpic_gbl_read()
770 case 0x00: /* Block Revision Register1 (BRR1) */ in openpic_gbl_read()
773 case 0x40: in openpic_gbl_read()
774 case 0x50: in openpic_gbl_read()
775 case 0x60: in openpic_gbl_read()
776 case 0x70: in openpic_gbl_read()
777 case 0x80: in openpic_gbl_read()
778 case 0x90: in openpic_gbl_read()
779 case 0xA0: in openpic_gbl_read()
780 case 0xB0: in openpic_gbl_read()
784 case 0x10A0: /* IPI_IVPR */ in openpic_gbl_read()
785 case 0x10B0: in openpic_gbl_read()
786 case 0x10C0: in openpic_gbl_read()
787 case 0x10D0: in openpic_gbl_read()
790 idx = (addr - 0x10A0) >> 4; in openpic_gbl_read()
794 case 0x10E0: /* SPVE */ in openpic_gbl_read()
802 pr_debug("%s: => 0x%08x\n", __func__, retval); in openpic_gbl_read()
812 addr += 0x10f0; in openpic_tmr_write()
815 if (addr & 0xF) in openpic_tmr_write()
816 return 0; in openpic_tmr_write()
818 if (addr == 0x10f0) { in openpic_tmr_write()
821 return 0; in openpic_tmr_write()
824 idx = (addr >> 6) & 0x3; in openpic_tmr_write()
825 addr = addr & 0x30; in openpic_tmr_write()
827 switch (addr & 0x30) { in openpic_tmr_write()
828 case 0x00: /* TCCR */ in openpic_tmr_write()
830 case 0x10: /* TBCR */ in openpic_tmr_write()
831 if ((opp->timers[idx].tccr & TCCR_TOG) != 0 && in openpic_tmr_write()
832 (val & TBCR_CI) == 0 && in openpic_tmr_write()
833 (opp->timers[idx].tbcr & TBCR_CI) != 0) in openpic_tmr_write()
838 case 0x20: /* TVPR */ in openpic_tmr_write()
841 case 0x30: /* TDR */ in openpic_tmr_write()
846 return 0; in openpic_tmr_write()
856 if (addr & 0xF) in openpic_tmr_read()
859 idx = (addr >> 6) & 0x3; in openpic_tmr_read()
860 if (addr == 0x0) { in openpic_tmr_read()
866 switch (addr & 0x30) { in openpic_tmr_read()
867 case 0x00: /* TCCR */ in openpic_tmr_read()
870 case 0x10: /* TBCR */ in openpic_tmr_read()
873 case 0x20: /* TIPV */ in openpic_tmr_read()
876 case 0x30: /* TIDE (TIDR) */ in openpic_tmr_read()
882 pr_debug("%s: => 0x%08x\n", __func__, retval); in openpic_tmr_read()
884 return 0; in openpic_tmr_read()
894 addr = addr & 0xffff; in openpic_src_write()
897 switch (addr & 0x1f) { in openpic_src_write()
898 case 0x00: in openpic_src_write()
901 case 0x10: in openpic_src_write()
904 case 0x18: in openpic_src_write()
909 return 0; in openpic_src_write()
919 retval = 0xFFFFFFFF; in openpic_src_read()
921 addr = addr & 0xffff; in openpic_src_read()
924 switch (addr & 0x1f) { in openpic_src_read()
925 case 0x00: in openpic_src_read()
928 case 0x10: in openpic_src_read()
931 case 0x18: in openpic_src_read()
936 pr_debug("%s: => 0x%08x\n", __func__, retval); in openpic_src_read()
938 return 0; in openpic_src_read()
947 pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val); in openpic_msi_write()
948 if (addr & 0xF) in openpic_msi_write()
949 return 0; in openpic_msi_write()
964 return 0; in openpic_msi_write()
970 uint32_t r = 0; in openpic_msi_read()
974 if (addr & 0xF) in openpic_msi_read()
980 case 0x00: in openpic_msi_read()
981 case 0x10: in openpic_msi_read()
982 case 0x20: in openpic_msi_read()
983 case 0x30: in openpic_msi_read()
984 case 0x40: in openpic_msi_read()
985 case 0x50: in openpic_msi_read()
986 case 0x60: in openpic_msi_read()
987 case 0x70: /* MSIRs */ in openpic_msi_read()
990 opp->msi[srs].msir = 0; in openpic_msi_read()
991 openpic_set_irq(opp, opp->irq_msi + srs, 0); in openpic_msi_read()
993 case 0x120: /* MSISR */ in openpic_msi_read()
994 for (i = 0; i < MAX_MSI; i++) in openpic_msi_read()
995 r |= (opp->msi[i].msir ? 1 : 0) << i; in openpic_msi_read()
999 pr_debug("%s: => 0x%08x\n", __func__, r); in openpic_msi_read()
1001 return 0; in openpic_msi_read()
1006 uint32_t r = 0; in openpic_summary_read()
1013 return 0; in openpic_summary_read()
1018 pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val); in openpic_summary_write()
1021 return 0; in openpic_summary_write()
1032 pr_debug("%s: cpu %d addr %#llx <= 0x%08x\n", __func__, idx, in openpic_cpu_write_internal()
1035 if (idx < 0) in openpic_cpu_write_internal()
1036 return 0; in openpic_cpu_write_internal()
1038 if (addr & 0xF) in openpic_cpu_write_internal()
1039 return 0; in openpic_cpu_write_internal()
1042 addr &= 0xFF0; in openpic_cpu_write_internal()
1044 case 0x40: /* IPIDR */ in openpic_cpu_write_internal()
1045 case 0x50: in openpic_cpu_write_internal()
1046 case 0x60: in openpic_cpu_write_internal()
1047 case 0x70: in openpic_cpu_write_internal()
1048 idx = (addr - 0x40) >> 4; in openpic_cpu_write_internal()
1052 openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); in openpic_cpu_write_internal()
1054 case 0x80: /* CTPR */ in openpic_cpu_write_internal()
1055 dst->ctpr = val & 0x0000000F; in openpic_cpu_write_internal()
1072 case 0x90: /* WHOAMI */ in openpic_cpu_write_internal()
1075 case 0xA0: /* IACK */ in openpic_cpu_write_internal()
1078 case 0xB0: { /* EOI */ in openpic_cpu_write_internal()
1084 if (s_IRQ < 0) { in openpic_cpu_write_internal()
1107 kvm_notify_acked_irq(opp->kvm, 0, notify_eoi); in openpic_cpu_write_internal()
1116 return 0; in openpic_cpu_write_internal()
1124 (addr & 0x1f000) >> 12); in openpic_cpu_write()
1146 pr_err("%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", in openpic_iack()
1159 src->pending = 0; in openpic_iack()
1168 openpic_set_irq(opp, irq, 0); in openpic_iack()
1199 retval = 0xFFFFFFFF; in openpic_cpu_read_internal()
1201 if (idx < 0) in openpic_cpu_read_internal()
1204 if (addr & 0xF) in openpic_cpu_read_internal()
1208 addr &= 0xFF0; in openpic_cpu_read_internal()
1210 case 0x80: /* CTPR */ in openpic_cpu_read_internal()
1213 case 0x90: /* WHOAMI */ in openpic_cpu_read_internal()
1216 case 0xA0: /* IACK */ in openpic_cpu_read_internal()
1219 case 0xB0: /* EOI */ in openpic_cpu_read_internal()
1220 retval = 0; in openpic_cpu_read_internal()
1225 pr_debug("%s: => 0x%08x\n", __func__, retval); in openpic_cpu_read_internal()
1229 return 0; in openpic_cpu_read_internal()
1237 (addr & 0x1f000) >> 12); in openpic_cpu_read()
1309 opp->vector_mask = 0xFFFF; in fsl_common_init()
1310 opp->tfrr_reset = 0; in fsl_common_init()
1312 opp->idr_reset = 1 << 0; in fsl_common_init()
1324 for (i = 0; i < opp->fsl->max_ext; i++) in fsl_common_init()
1344 for (i = 0; i < opp->num_mmio_regions; i++) { in kvm_mpic_read_internal()
1360 for (i = 0; i < opp->num_mmio_regions; i++) { in kvm_mpic_write_internal()
1467 if (base & 0x3ffff) { in set_base_addr()
1474 return 0; in set_base_addr()
1484 if (base == 0) in set_base_addr()
1491 return 0; in set_base_addr()
1494 #define ATTR_SET 0
1545 if (attr32 != 0 && attr32 != 1) in mpic_set_attr()
1551 return 0; in mpic_set_attr()
1576 return 0; in mpic_get_attr()
1589 return 0; in mpic_get_attr()
1602 return 0; in mpic_get_attr()
1614 return 0; in mpic_has_attr()
1620 return 0; in mpic_has_attr()
1626 return 0; in mpic_has_attr()
1650 kvm_set_irq_routing(opp->kvm, routing, 0, 0); in mpic_set_default_irq_routing()
1653 return 0; in mpic_set_default_irq_routing()
1683 opp->brr1 = 0x00400200; in mpic_create()
1694 opp->brr1 = 0x00400402; in mpic_create()
1717 return 0; in mpic_create()
1737 int ret = 0; in kvmppc_mpic_connect_vcpu()
1743 if (cpu < 0 || cpu >= MAX_CPU) in kvmppc_mpic_connect_vcpu()
1787 * < 0 Interrupt was ignored (masked or not delivered for other reasons)
1788 * = 0 Interrupt was coalesced (previous irq is still pending)
1789 * > 0 Number of CPUs interrupt was delivered to
1804 return 0; in mpic_set_irq()
1823 return 0; in kvm_set_msi()
1850 r = 0; in kvm_set_routing_entry()