Lines Matching +full:0 +full:x1234
18 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
31 ___PPC_RA(base) | ((i) & 0xfffc))
58 memset(regs, 0, sizeof(struct pt_regs)); in init_pt_regs()
65 asm volatile("mfmsr %0" : "=r"(regs->msr)); in init_pt_regs()
83 unsigned long a = 0x23; in test_ld()
89 /* ld r5, 0(r3) */ in test_ld()
90 stepped = emulate_step(®s, TEST_LD(5, 3, 0)); in test_ld()
101 unsigned int a = 0x4545; in test_lwz()
107 /* lwz r5, 0(r3) */ in test_lwz()
108 stepped = emulate_step(®s, TEST_LWZ(5, 3, 0)); in test_lwz()
119 unsigned int a[3] = {0x0, 0x0, 0x1234}; in test_lwzx()
125 regs.gpr[5] = 0x8765; in test_lwzx()
138 unsigned long a = 0x1234; in test_std()
143 regs.gpr[5] = 0x5678; in test_std()
145 /* std r5, 0(r3) */ in test_std()
146 stepped = emulate_step(®s, TEST_STD(5, 3, 0)); in test_std()
156 unsigned long a = 0x1234; in test_ldarx_stdcx()
158 unsigned long cr0_eq = 0x1 << 29; /* eq bit of CR0 */ in test_ldarx_stdcx()
161 asm volatile("mfcr %0" : "=r"(regs.ccr)); in test_ldarx_stdcx()
167 regs.gpr[4] = 0; in test_ldarx_stdcx()
168 regs.gpr[5] = 0x5678; in test_ldarx_stdcx()
170 /* ldarx r5, r3, r4, 0 */ in test_ldarx_stdcx()
171 stepped = emulate_step(®s, TEST_LDARX(5, 3, 4, 0)); in test_ldarx_stdcx()
178 if (stepped <= 0 || regs.gpr[5] != 0x1234) { in test_ldarx_stdcx()
186 regs.gpr[5] = 0x9ABC; in test_ldarx_stdcx()
197 * In this case cr0.eq bit will be set to 0. in test_ldarx_stdcx()
226 regs.gpr[4] = 0; in test_lfsx_stfsx()
269 regs.gpr[4] = 0; in test_lfdx_stfdx()
322 cached_b[0] = c.b[0] = 923745; in test_lvx_stvx()
328 regs.gpr[4] = 0; in test_lvx_stvx()
341 c.b[0] = 4987513; in test_lvx_stvx()
349 if (stepped == 1 && cached_b[0] == c.b[0] && cached_b[1] == c.b[1] && in test_lvx_stvx()
379 cached_b[0] = c.b[0] = 18233; in test_lxvd2x_stxvd2x()
385 regs.gpr[4] = 0; in test_lxvd2x_stxvd2x()
402 c.b[0] = 21379463; in test_lxvd2x_stxvd2x()
410 if (stepped == 1 && cached_b[0] == c.b[0] && cached_b[1] == c.b[1] && in test_lxvd2x_stxvd2x()
441 return 0; in test_emulate_step()