Lines Matching +full:1 +full:c
44 * MMCR1[25] = pmc1combine[1]
46 * MMCR1[27] = pmc2combine[1]
48 * MMCR1[29] = pmc3combine[1]
50 * MMCR1[31] = pmc4combine[1]
67 * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL)
70 * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0)
71 * else if cache_sel[0] == 1:
73 * else if cache_sel[1]: # L1 event
78 * MMCRA[63] = 1 (SAMPLE_ENABLE)
293 return -1; in power9_bhrb_filter_map()
296 return -1; in power9_bhrb_filter_map()
299 return -1; in power9_bhrb_filter_map()
307 return -1; in power9_bhrb_filter_map()
318 #define C(x) PERF_COUNT_HW_CACHE_##x macro
322 * 0 means not supported, -1 means nonsensical, other values
325 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
326 [ C(L1D) ] = {
327 [ C(OP_READ) ] = {
328 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
329 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
331 [ C(OP_WRITE) ] = {
332 [ C(RESULT_ACCESS) ] = 0,
333 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
335 [ C(OP_PREFETCH) ] = {
336 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
337 [ C(RESULT_MISS) ] = 0,
340 [ C(L1I) ] = {
341 [ C(OP_READ) ] = {
342 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
343 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
345 [ C(OP_WRITE) ] = {
346 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
347 [ C(RESULT_MISS) ] = -1,
349 [ C(OP_PREFETCH) ] = {
350 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
351 [ C(RESULT_MISS) ] = 0,
354 [ C(LL) ] = {
355 [ C(OP_READ) ] = {
356 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
357 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
359 [ C(OP_WRITE) ] = {
360 [ C(RESULT_ACCESS) ] = PM_L2_ST,
361 [ C(RESULT_MISS) ] = PM_L2_ST_MISS,
363 [ C(OP_PREFETCH) ] = {
364 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
365 [ C(RESULT_MISS) ] = 0,
368 [ C(DTLB) ] = {
369 [ C(OP_READ) ] = {
370 [ C(RESULT_ACCESS) ] = 0,
371 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
373 [ C(OP_WRITE) ] = {
374 [ C(RESULT_ACCESS) ] = -1,
375 [ C(RESULT_MISS) ] = -1,
377 [ C(OP_PREFETCH) ] = {
378 [ C(RESULT_ACCESS) ] = -1,
379 [ C(RESULT_MISS) ] = -1,
382 [ C(ITLB) ] = {
383 [ C(OP_READ) ] = {
384 [ C(RESULT_ACCESS) ] = 0,
385 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
387 [ C(OP_WRITE) ] = {
388 [ C(RESULT_ACCESS) ] = -1,
389 [ C(RESULT_MISS) ] = -1,
391 [ C(OP_PREFETCH) ] = {
392 [ C(RESULT_ACCESS) ] = -1,
393 [ C(RESULT_MISS) ] = -1,
396 [ C(BPU) ] = {
397 [ C(OP_READ) ] = {
398 [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
399 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
401 [ C(OP_WRITE) ] = {
402 [ C(RESULT_ACCESS) ] = -1,
403 [ C(RESULT_MISS) ] = -1,
405 [ C(OP_PREFETCH) ] = {
406 [ C(RESULT_ACCESS) ] = -1,
407 [ C(RESULT_MISS) ] = -1,
410 [ C(NODE) ] = {
411 [ C(OP_READ) ] = {
412 [ C(RESULT_ACCESS) ] = -1,
413 [ C(RESULT_MISS) ] = -1,
415 [ C(OP_WRITE) ] = {
416 [ C(RESULT_ACCESS) ] = -1,
417 [ C(RESULT_MISS) ] = -1,
419 [ C(OP_PREFETCH) ] = {
420 [ C(RESULT_ACCESS) ] = -1,
421 [ C(RESULT_MISS) ] = -1,
426 #undef C
461 if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) { in init_power9_pmu()