Lines Matching +full:0 +full:x349
80 #define HAMMERHEAD_BASE 0xf8000000
81 #define HHEAD_CONFIG 0x90
82 #define HHEAD_SEC_INTR 0xc0
86 #define PSURGE_PRI_INTR 0xf3019000
90 #define PSURGE_START 0xf2800000
93 #define PSURGE_QUAD_REG_ADDR 0xf8800000
95 #define PSURGE_QUAD_IRQ_SET 0
106 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
119 #define PSURGE_DUAL 0
138 if (cpu == 0) in psurge_set_ipi()
141 out_8(psurge_sec_intr, 0); in psurge_set_ipi()
148 if (cpu > 0) { in psurge_clr_ipi()
151 out_8(psurge_sec_intr, ~0); in psurge_clr_ipi()
184 return 0; in psurge_host_map()
195 psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL); in psurge_secondary_ipi_init()
228 for (i = 0; i < 100; i++) { in psurge_quad_probe()
230 bogus[(0+i)%8] = 0x00000000; in psurge_quad_probe()
231 bogus[(1+i)%8] = 0x55555555; in psurge_quad_probe()
232 bogus[(2+i)%8] = 0xFFFFFFFF; in psurge_quad_probe()
233 bogus[(3+i)%8] = 0xAAAAAAAA; in psurge_quad_probe()
234 bogus[(4+i)%8] = 0x33333333; in psurge_quad_probe()
235 bogus[(5+i)%8] = 0xCCCCCCCC; in psurge_quad_probe()
236 bogus[(6+i)%8] = 0xCCCCCCCC; in psurge_quad_probe()
237 bogus[(7+i)%8] = 0x33333333; in psurge_quad_probe()
239 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); in psurge_quad_probe()
251 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); in psurge_quad_init()
258 out_8(psurge_sec_intr, ~0); in psurge_quad_init()
295 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); in smp_psurge_probe()
309 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { in smp_psurge_probe()
334 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); in smp_psurge_probe()
350 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) in smp_psurge_kick_cpu()
351 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); in smp_psurge_kick_cpu()
354 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); in smp_psurge_kick_cpu()
367 for (i = 0; i < 2000; ++i) in smp_psurge_kick_cpu()
376 for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { in smp_psurge_kick_cpu()
388 tb_req = 0; in smp_psurge_kick_cpu()
401 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); in smp_psurge_kick_cpu()
403 return 0; in smp_psurge_kick_cpu()
414 if (cpu_nr != 0 || !psurge_start) in smp_psurge_setup_cpu()
419 out_be32(psurge_start, 0x100); in smp_psurge_setup_cpu()
434 set_tb(timebase >> 32, timebase & 0xffffffff); in smp_psurge_take_timebase()
435 timebase = 0; in smp_psurge_take_timebase()
471 tb_req = 0; in smp_core99_give_timebase()
479 (*pmac_tb_freeze)(0); in smp_core99_give_timebase()
497 set_tb(timebase >> 32, timebase & 0xffffffff); in smp_core99_take_timebase()
498 timebase = 0; in smp_core99_take_timebase()
516 /* Strangely, the device-tree says address is 0xd2, but darwin in smp_core99_cypress_tb_freeze()
517 * accesses 0xd0 ... in smp_core99_cypress_tb_freeze()
522 0xd0 | pmac_i2c_read, in smp_core99_cypress_tb_freeze()
523 1, 0x81, &data, 1); in smp_core99_cypress_tb_freeze()
524 if (rc != 0) in smp_core99_cypress_tb_freeze()
527 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); in smp_core99_cypress_tb_freeze()
531 0xd0 | pmac_i2c_write, in smp_core99_cypress_tb_freeze()
532 1, 0x81, &data, 1); in smp_core99_cypress_tb_freeze()
535 if (rc != 0) { in smp_core99_cypress_tb_freeze()
552 1, 0x2e, &data, 1); in smp_core99_pulsar_tb_freeze()
553 if (rc != 0) in smp_core99_pulsar_tb_freeze()
556 data = (data & 0x88) | (freeze ? 0x11 : 0x22); in smp_core99_pulsar_tb_freeze()
561 1, 0x2e, &data, 1); in smp_core99_pulsar_tb_freeze()
563 if (rc != 0) { in smp_core99_pulsar_tb_freeze()
593 case 0xd2: in smp_core99_setup_i2c_hwsync()
596 pmac_tb_pulsar_addr = 0xd2; in smp_core99_setup_i2c_hwsync()
603 case 0xd4: in smp_core99_setup_i2c_hwsync()
605 pmac_tb_pulsar_addr = 0xd4; in smp_core99_setup_i2c_hwsync()
642 args.u[0].v = !freeze; in smp_core99_pfunc_tb_freeze()
660 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); in smp_core99_gpio_tb_freeze()
661 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); in smp_core99_gpio_tb_freeze()
677 if (cpu == 0) { in core99_init_caches()
682 _set_L2CR(0); in core99_init_caches()
690 if (cpu == 0){ in core99_init_caches()
695 _set_L3CR(0); in core99_init_caches()
741 " GPIO 0x%02x\n", core99_tb_gpio); in smp_core99_setup()
765 powersave_nap = 0; in smp_core99_setup()
771 int ncpus = 0; in smp_core99_probe()
773 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); in smp_core99_probe()
797 /* Collect l2cr and l3cr values from CPU 0 */ in smp_core99_probe()
798 core99_init_caches(0); in smp_core99_probe()
805 unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100); in smp_core99_kick_cpu()
807 if (nr < 0 || nr > 3) in smp_core99_kick_cpu()
811 ppc_md.progress("smp_core99_kick_cpu", 0x346); in smp_core99_kick_cpu()
825 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); in smp_core99_kick_cpu()
839 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); in smp_core99_kick_cpu()
841 return 0; in smp_core99_kick_cpu()
847 if (cpu_nr != 0) in smp_core99_setup_cpu()
871 return 0; in smp_core99_cpu_prepare()
879 smp_core99_host_open = 0; in smp_core99_cpu_online()
881 return 0; in smp_core99_cpu_online()
910 ppc_md.progress("smp_core99_bringup_done", 0x349); in smp_core99_bringup_done()
922 mpic_cpu_set_priority(0xf); in smp_core99_cpu_disable()
924 return 0; in smp_core99_cpu_disable()
972 set_dec(0x7fffffff); in pmac_cpu_die()