Lines Matching +full:port +full:- +full:phys
6 * - fixed maintenance access routines, check for aligned access
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
15 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
28 #include <linux/dma-mapping.h>
37 (((struct rio_priv *)(mport->priv))->rmm_handle)
39 /* RapidIO definition irq, which read from OF-tree */
40 #define IRQ_RIO_PW(m) (((struct fsl_rio_pw *)(m))->pwirq)
41 #define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq)
42 #define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq)
43 #define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq)
168 dma_addr_t phys; member
178 dma_addr_t phys; member
201 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
203 * @dev_instance: Pointer to interrupt-specific data
212 struct rio_mport *port = (struct rio_mport *)dev_instance; in fsl_rio_tx_handler() local
213 struct fsl_rmu *rmu = GET_RMM_HANDLE(port); in fsl_rio_tx_handler()
215 osr = in_be32(&rmu->msg_regs->osr); in fsl_rio_tx_handler()
219 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE); in fsl_rio_tx_handler()
225 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI); in fsl_rio_tx_handler()
230 u32 dqp = in_be32(&rmu->msg_regs->odqdpar); in fsl_rio_tx_handler()
231 int slot = (dqp - rmu->msg_tx_ring.phys) >> 5; in fsl_rio_tx_handler()
232 if (port->outb_msg[0].mcback != NULL) { in fsl_rio_tx_handler()
233 port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id, in fsl_rio_tx_handler()
234 -1, in fsl_rio_tx_handler()
237 /* Ack the end-of-message interrupt */ in fsl_rio_tx_handler()
238 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI); in fsl_rio_tx_handler()
246 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
248 * @dev_instance: Pointer to interrupt-specific data
257 struct rio_mport *port = (struct rio_mport *)dev_instance; in fsl_rio_rx_handler() local
258 struct fsl_rmu *rmu = GET_RMM_HANDLE(port); in fsl_rio_rx_handler()
260 isr = in_be32(&rmu->msg_regs->isr); in fsl_rio_rx_handler()
264 out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE); in fsl_rio_rx_handler()
275 if (port->inb_msg[0].mcback != NULL) in fsl_rio_rx_handler()
276 port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id, in fsl_rio_rx_handler()
277 -1, in fsl_rio_rx_handler()
278 -1); in fsl_rio_rx_handler()
281 out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI); in fsl_rio_rx_handler()
289 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
291 * @dev_instance: Pointer to interrupt-specific data
303 dsr = in_be32(&fsl_dbell->dbell_regs->dsr); in fsl_rio_dbell_handler()
307 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_TE); in fsl_rio_dbell_handler()
313 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_QFI); in fsl_rio_dbell_handler()
319 fsl_dbell->dbell_ring.virt + in fsl_rio_dbell_handler()
320 (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff); in fsl_rio_dbell_handler()
327 dmsg->sid, dmsg->tid, dmsg->info); in fsl_rio_dbell_handler()
330 if (fsl_dbell->mport[i]) { in fsl_rio_dbell_handler()
332 &fsl_dbell->mport[i]->dbells, node) { in fsl_rio_dbell_handler()
333 if ((dbell->res->start in fsl_rio_dbell_handler()
334 <= dmsg->info) in fsl_rio_dbell_handler()
335 && (dbell->res->end in fsl_rio_dbell_handler()
336 >= dmsg->info)) { in fsl_rio_dbell_handler()
341 if (found && dbell->dinb) { in fsl_rio_dbell_handler()
342 dbell->dinb(fsl_dbell->mport[i], in fsl_rio_dbell_handler()
343 dbell->dev_id, dmsg->sid, in fsl_rio_dbell_handler()
344 dmsg->tid, in fsl_rio_dbell_handler()
345 dmsg->info); in fsl_rio_dbell_handler()
355 dmsg->sid, dmsg->tid, in fsl_rio_dbell_handler()
356 dmsg->info); in fsl_rio_dbell_handler()
358 setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); in fsl_rio_dbell_handler()
359 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI); in fsl_rio_dbell_handler()
377 out_be32(&dbell->dbell_regs->odsr, ODSR_CLEAR); in msg_unit_error_handler()
378 out_be32(&dbell->dbell_regs->dsr, IDSR_CLEAR); in msg_unit_error_handler()
380 out_be32(&pw->pw_regs->pwsr, IPWSR_CLEAR); in msg_unit_error_handler()
384 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
386 * @dev_instance: Pointer to interrupt-specific data
388 * Handles port write interrupts. Parses a list of registered
389 * port write event handlers and executes a matching event handler.
402 ipwmr = in_be32(&pw->pw_regs->pwmr); in fsl_rio_port_write_handler()
403 ipwsr = in_be32(&pw->pw_regs->pwsr); in fsl_rio_port_write_handler()
406 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); in fsl_rio_port_write_handler()
424 if (kfifo_avail(&pw->pw_fifo) >= RIO_PW_MSG_SIZE) { in fsl_rio_port_write_handler()
425 pw->port_write_msg.msg_count++; in fsl_rio_port_write_handler()
426 kfifo_in(&pw->pw_fifo, pw->port_write_msg.virt, in fsl_rio_port_write_handler()
429 pw->port_write_msg.discard_count++; in fsl_rio_port_write_handler()
430 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", in fsl_rio_port_write_handler()
431 pw->port_write_msg.discard_count); in fsl_rio_port_write_handler()
434 * another port-write to be received. in fsl_rio_port_write_handler()
436 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_QFI); in fsl_rio_port_write_handler()
437 out_be32(&pw->pw_regs->pwmr, ipwmr | RIO_IPWMR_CQ); in fsl_rio_port_write_handler()
439 schedule_work(&pw->pw_work); in fsl_rio_port_write_handler()
443 pw->port_write_msg.err_count++; in fsl_rio_port_write_handler()
444 pr_debug("RIO: Port-Write Transaction Err (%d)\n", in fsl_rio_port_write_handler()
445 pw->port_write_msg.err_count); in fsl_rio_port_write_handler()
446 /* Clear Transaction Error: port-write controller should be in fsl_rio_port_write_handler()
449 out_be32(&pw->pw_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); in fsl_rio_port_write_handler()
450 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_TE); in fsl_rio_port_write_handler()
451 out_be32(&pw->pw_regs->pwmr, ipwmr); in fsl_rio_port_write_handler()
455 pw->port_write_msg.discard_count++; in fsl_rio_port_write_handler()
456 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", in fsl_rio_port_write_handler()
457 pw->port_write_msg.discard_count); in fsl_rio_port_write_handler()
458 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_PWD); in fsl_rio_port_write_handler()
490 * Process port-write messages in fsl_pw_dpc()
492 while (kfifo_out_spinlocked(&pw->pw_fifo, (unsigned char *)&msg_buffer, in fsl_pw_dpc()
493 RIO_PW_MSG_SIZE, &pw->pw_fifo_lock)) { in fsl_pw_dpc()
497 pr_debug("%s : Port-Write Message:", __func__); in fsl_pw_dpc()
508 /* Pass the port-write message to RIO core for processing */ in fsl_pw_dpc()
510 if (pw->mport[i]) in fsl_pw_dpc()
511 rio_inb_pwrite_handler(pw->mport[i], in fsl_pw_dpc()
518 * fsl_rio_pw_enable - enable/disable port-write interface init
519 * @mport: Master port implementing the port write unit
520 * @enable: 1=enable; 0=disable port-write message handling
526 rval = in_be32(&pw->pw_regs->pwmr); in fsl_rio_pw_enable()
533 out_be32(&pw->pw_regs->pwmr, rval); in fsl_rio_pw_enable()
539 * fsl_rio_port_write_init - MPC85xx port write interface init
540 * @mport: Master port implementing the port write unit
542 * Initializes port write unit hardware and DMA buffer
544 * or %-ENOMEM on failure.
551 /* Following configurations require a disabled port write controller */ in fsl_rio_port_write_init()
552 out_be32(&pw->pw_regs->pwmr, in fsl_rio_port_write_init()
553 in_be32(&pw->pw_regs->pwmr) & ~RIO_IPWMR_PWE); in fsl_rio_port_write_init()
555 /* Initialize port write */ in fsl_rio_port_write_init()
556 pw->port_write_msg.virt = dma_alloc_coherent(pw->dev, in fsl_rio_port_write_init()
558 &pw->port_write_msg.phys, GFP_KERNEL); in fsl_rio_port_write_init()
559 if (!pw->port_write_msg.virt) { in fsl_rio_port_write_init()
560 pr_err("RIO: unable allocate port write queue\n"); in fsl_rio_port_write_init()
561 return -ENOMEM; in fsl_rio_port_write_init()
564 pw->port_write_msg.err_count = 0; in fsl_rio_port_write_init()
565 pw->port_write_msg.discard_count = 0; in fsl_rio_port_write_init()
568 out_be32(&pw->pw_regs->epwqbar, 0); in fsl_rio_port_write_init()
569 out_be32(&pw->pw_regs->pwqbar, (u32) pw->port_write_msg.phys); in fsl_rio_port_write_init()
572 in_be32(&pw->pw_regs->epwqbar), in fsl_rio_port_write_init()
573 in_be32(&pw->pw_regs->pwqbar)); in fsl_rio_port_write_init()
576 out_be32(&pw->pw_regs->pwsr, in fsl_rio_port_write_init()
579 /* Configure port write controller for snooping enable all reporting, in fsl_rio_port_write_init()
581 out_be32(&pw->pw_regs->pwmr, in fsl_rio_port_write_init()
585 /* Hook up port-write handler */ in fsl_rio_port_write_init()
587 IRQF_SHARED, "port-write", (void *)pw); in fsl_rio_port_write_init()
595 INIT_WORK(&pw->pw_work, fsl_pw_dpc); in fsl_rio_port_write_init()
596 spin_lock_init(&pw->pw_fifo_lock); in fsl_rio_port_write_init()
597 if (kfifo_alloc(&pw->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { in fsl_rio_port_write_init()
599 rc = -ENOMEM; in fsl_rio_port_write_init()
604 in_be32(&pw->pw_regs->pwmr), in fsl_rio_port_write_init()
605 in_be32(&pw->pw_regs->pwsr)); in fsl_rio_port_write_init()
612 dma_free_coherent(pw->dev, RIO_PW_MSG_SIZE, in fsl_rio_port_write_init()
613 pw->port_write_msg.virt, in fsl_rio_port_write_init()
614 pw->port_write_msg.phys); in fsl_rio_port_write_init()
619 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
620 * @mport: RapidIO master port info
623 * @data: 16-bit info field of RapidIO doorbell message
626 * %-EINVAL on failure.
641 out_be32(&dbell->dbell_regs->odmr, 0x00000000); in fsl_rio_doorbell_send()
642 out_be32(&dbell->dbell_regs->odretcr, 0x00000004); in fsl_rio_doorbell_send()
643 out_be32(&dbell->dbell_regs->oddpr, destid << 16); in fsl_rio_doorbell_send()
644 out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data); in fsl_rio_doorbell_send()
645 out_be32(&dbell->dbell_regs->odmr, 0x00000001); in fsl_rio_doorbell_send()
653 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
654 * @mport: Master port with outbound message queue
661 * %0 on success or %-EINVAL on failure.
669 struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt in fsl_add_outb_message()
670 + rmu->msg_tx_ring.tx_slot; in fsl_add_outb_message()
674 "%p len %8.8zx\n", rdev->destid, mbox, buffer, len); in fsl_add_outb_message()
676 ret = -EINVAL; in fsl_add_outb_message()
681 memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer, in fsl_add_outb_message()
683 if (len < (RIO_MAX_MSG_SIZE - 4)) in fsl_add_outb_message()
684 memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot] in fsl_add_outb_message()
685 + len, 0, RIO_MAX_MSG_SIZE - len); in fsl_add_outb_message()
688 desc->dport = (rdev->destid << 16) | (mbox & 0x3); in fsl_add_outb_message()
691 desc->dattr = 0x28000000 | ((mport->index) << 20); in fsl_add_outb_message()
694 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); in fsl_add_outb_message()
697 desc->saddr = 0x00000004 in fsl_add_outb_message()
698 | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot]; in fsl_add_outb_message()
701 omr = in_be32(&rmu->msg_regs->omr); in fsl_add_outb_message()
702 out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI); in fsl_add_outb_message()
705 if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size) in fsl_add_outb_message()
706 rmu->msg_tx_ring.tx_slot = 0; in fsl_add_outb_message()
713 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
714 * @mport: Master port implementing the outbound message unit
721 * %-EINVAL or %-ENOMEM on failure.
727 struct rio_priv *priv = mport->priv; in fsl_open_outb_mbox()
732 rc = -EINVAL; in fsl_open_outb_mbox()
737 rmu->msg_tx_ring.dev_id = dev_id; in fsl_open_outb_mbox()
738 rmu->msg_tx_ring.size = entries; in fsl_open_outb_mbox()
740 for (i = 0; i < rmu->msg_tx_ring.size; i++) { in fsl_open_outb_mbox()
741 rmu->msg_tx_ring.virt_buffer[i] = in fsl_open_outb_mbox()
742 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, in fsl_open_outb_mbox()
743 &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL); in fsl_open_outb_mbox()
744 if (!rmu->msg_tx_ring.virt_buffer[i]) { in fsl_open_outb_mbox()
745 rc = -ENOMEM; in fsl_open_outb_mbox()
746 for (j = 0; j < rmu->msg_tx_ring.size; j++) in fsl_open_outb_mbox()
747 if (rmu->msg_tx_ring.virt_buffer[j]) in fsl_open_outb_mbox()
748 dma_free_coherent(priv->dev, in fsl_open_outb_mbox()
750 rmu->msg_tx_ring. in fsl_open_outb_mbox()
752 rmu->msg_tx_ring. in fsl_open_outb_mbox()
759 rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, in fsl_open_outb_mbox()
760 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, in fsl_open_outb_mbox()
761 &rmu->msg_tx_ring.phys, GFP_KERNEL); in fsl_open_outb_mbox()
762 if (!rmu->msg_tx_ring.virt) { in fsl_open_outb_mbox()
763 rc = -ENOMEM; in fsl_open_outb_mbox()
766 memset(rmu->msg_tx_ring.virt, 0, in fsl_open_outb_mbox()
767 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE); in fsl_open_outb_mbox()
768 rmu->msg_tx_ring.tx_slot = 0; in fsl_open_outb_mbox()
771 out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys); in fsl_open_outb_mbox()
772 out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys); in fsl_open_outb_mbox()
775 out_be32(&rmu->msg_regs->osar, 0x00000004); in fsl_open_outb_mbox()
778 out_be32(&rmu->msg_regs->osr, 0x000000b3); in fsl_open_outb_mbox()
793 out_be32(&rmu->msg_regs->omr, 0x00100220); in fsl_open_outb_mbox()
796 out_be32(&rmu->msg_regs->omr, in fsl_open_outb_mbox()
797 in_be32(&rmu->msg_regs->omr) | in fsl_open_outb_mbox()
798 ((get_bitmask_order(entries) - 2) << 12)); in fsl_open_outb_mbox()
801 out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1); in fsl_open_outb_mbox()
807 dma_free_coherent(priv->dev, in fsl_open_outb_mbox()
808 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, in fsl_open_outb_mbox()
809 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); in fsl_open_outb_mbox()
812 for (i = 0; i < rmu->msg_tx_ring.size; i++) in fsl_open_outb_mbox()
813 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, in fsl_open_outb_mbox()
814 rmu->msg_tx_ring.virt_buffer[i], in fsl_open_outb_mbox()
815 rmu->msg_tx_ring.phys_buffer[i]); in fsl_open_outb_mbox()
821 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
822 * @mport: Master port implementing the outbound message unit
830 struct rio_priv *priv = mport->priv; in fsl_close_outb_mbox()
834 out_be32(&rmu->msg_regs->omr, 0); in fsl_close_outb_mbox()
837 dma_free_coherent(priv->dev, in fsl_close_outb_mbox()
838 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, in fsl_close_outb_mbox()
839 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); in fsl_close_outb_mbox()
846 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
847 * @mport: Master port implementing the inbound message unit
854 * and %-EINVAL or %-ENOMEM on failure.
860 struct rio_priv *priv = mport->priv; in fsl_open_inb_mbox()
865 rc = -EINVAL; in fsl_open_inb_mbox()
870 rmu->msg_rx_ring.dev_id = dev_id; in fsl_open_inb_mbox()
871 rmu->msg_rx_ring.size = entries; in fsl_open_inb_mbox()
872 rmu->msg_rx_ring.rx_slot = 0; in fsl_open_inb_mbox()
873 for (i = 0; i < rmu->msg_rx_ring.size; i++) in fsl_open_inb_mbox()
874 rmu->msg_rx_ring.virt_buffer[i] = NULL; in fsl_open_inb_mbox()
877 rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, in fsl_open_inb_mbox()
878 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, in fsl_open_inb_mbox()
879 &rmu->msg_rx_ring.phys, GFP_KERNEL); in fsl_open_inb_mbox()
880 if (!rmu->msg_rx_ring.virt) { in fsl_open_inb_mbox()
881 rc = -ENOMEM; in fsl_open_inb_mbox()
886 out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys); in fsl_open_inb_mbox()
887 out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys); in fsl_open_inb_mbox()
890 out_be32(&rmu->msg_regs->isr, 0x00000091); in fsl_open_inb_mbox()
896 dma_free_coherent(priv->dev, in fsl_open_inb_mbox()
897 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, in fsl_open_inb_mbox()
898 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys); in fsl_open_inb_mbox()
909 out_be32(&rmu->msg_regs->imr, 0x001b0060); in fsl_open_inb_mbox()
912 setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); in fsl_open_inb_mbox()
915 setbits32(&rmu->msg_regs->imr, 0x1); in fsl_open_inb_mbox()
922 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
923 * @mport: Master port implementing the inbound message unit
931 struct rio_priv *priv = mport->priv; in fsl_close_inb_mbox()
935 out_be32(&rmu->msg_regs->imr, 0); in fsl_close_inb_mbox()
938 dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, in fsl_close_inb_mbox()
939 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys); in fsl_close_inb_mbox()
946 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
947 * @mport: Master port implementing the inbound message unit
952 * %0 on success or %-EINVAL on failure.
960 rmu->msg_rx_ring.rx_slot); in fsl_add_inb_buffer()
962 if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) { in fsl_add_inb_buffer()
965 rmu->msg_rx_ring.rx_slot); in fsl_add_inb_buffer()
966 rc = -EINVAL; in fsl_add_inb_buffer()
970 rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf; in fsl_add_inb_buffer()
971 if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size) in fsl_add_inb_buffer()
972 rmu->msg_rx_ring.rx_slot = 0; in fsl_add_inb_buffer()
979 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
980 * @mport: Master port implementing the inbound message unit
994 phys_buf = in_be32(&rmu->msg_regs->ifqdpar); in fsl_get_inb_message()
997 if (phys_buf == in_be32(&rmu->msg_regs->ifqepar)) in fsl_get_inb_message()
1000 virt_buf = rmu->msg_rx_ring.virt + (phys_buf in fsl_get_inb_message()
1001 - rmu->msg_rx_ring.phys); in fsl_get_inb_message()
1002 buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; in fsl_get_inb_message()
1003 buf = rmu->msg_rx_ring.virt_buffer[buf_idx]; in fsl_get_inb_message()
1015 rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL; in fsl_get_inb_message()
1018 setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); in fsl_get_inb_message()
1025 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1026 * @mport: Master port implementing the inbound doorbell unit
1030 * or %-ENOMEM on failure.
1037 dbell->dbell_ring.virt = dma_alloc_coherent(dbell->dev, 512 * in fsl_rio_doorbell_init()
1038 DOORBELL_MESSAGE_SIZE, &dbell->dbell_ring.phys, GFP_KERNEL); in fsl_rio_doorbell_init()
1039 if (!dbell->dbell_ring.virt) { in fsl_rio_doorbell_init()
1041 rc = -ENOMEM; in fsl_rio_doorbell_init()
1046 out_be32(&dbell->dbell_regs->dqdpar, (u32) dbell->dbell_ring.phys); in fsl_rio_doorbell_init()
1047 out_be32(&dbell->dbell_regs->dqepar, (u32) dbell->dbell_ring.phys); in fsl_rio_doorbell_init()
1050 out_be32(&dbell->dbell_regs->dsr, 0x00000091); in fsl_rio_doorbell_init()
1056 dma_free_coherent(dbell->dev, 512 * DOORBELL_MESSAGE_SIZE, in fsl_rio_doorbell_init()
1057 dbell->dbell_ring.virt, dbell->dbell_ring.phys); in fsl_rio_doorbell_init()
1064 out_be32(&dbell->dbell_regs->dmr, 0x00108161); in fsl_rio_doorbell_init()
1079 if (!mport || !mport->priv) in fsl_rio_setup_rmu()
1080 return -EINVAL; in fsl_rio_setup_rmu()
1082 priv = mport->priv; in fsl_rio_setup_rmu()
1085 dev_warn(priv->dev, "Can't get %pOF property 'fsl,rmu'\n", in fsl_rio_setup_rmu()
1086 priv->dev->of_node); in fsl_rio_setup_rmu()
1087 return -EINVAL; in fsl_rio_setup_rmu()
1092 return -ENOMEM; in fsl_rio_setup_rmu()
1097 pr_err("%pOF: unable to find 'reg' property of message-unit\n", in fsl_rio_setup_rmu()
1100 return -ENOMEM; in fsl_rio_setup_rmu()
1104 rmu->msg_regs = (struct rio_msg_regs *) in fsl_rio_setup_rmu()
1107 rmu->txirq = irq_of_parse_and_map(node, 0); in fsl_rio_setup_rmu()
1108 rmu->rxirq = irq_of_parse_and_map(node, 1); in fsl_rio_setup_rmu()
1110 node, rmu->txirq, rmu->rxirq); in fsl_rio_setup_rmu()
1112 priv->rmm_handle = rmu; in fsl_rio_setup_rmu()
1114 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); in fsl_rio_setup_rmu()
1115 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0); in fsl_rio_setup_rmu()
1116 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); in fsl_rio_setup_rmu()