Lines Matching +full:0 +full:x1c000000
35 * SW2 0x1x xxxx -> little endian
42 * 0x00000000 - 0x04000000 (CS0) Nor Flash
43 * 0x04000000 - 0x04200000 (CS1) SRAM
44 * 0x05000000 - 0x05800000 (CS1) on board register
45 * 0x05800000 - 0x06000000 (CS1) LAN91C111
46 * 0x06000000 - 0x06400000 (CS1) PCMCIA
47 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
48 * 0x10000000 - 0x14000000 (CS4) PCIe
49 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
50 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
51 * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash
52 * 0x1C000000 - (CS7) SH7786 Control register
75 [0] = {
77 .start = 0x05800300,
78 .end = 0x0580030f,
82 .start = evt2irq(0x360),
100 .offset = 0x00000000,
129 [0] = {
158 __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001, in urquell_devices_setup()
168 __raw_writew(0xa5a5, UBOARDREG(SRSTR)); in urquell_power_off()