Lines Matching full:values

29 #define PCISH5_ICR_CR          0x100   /* PCI control register values */
45 #define PCISH5_ICR_INT         0x114   /* Interrupt registert values     */
48 #define PCISH5_ICR_LSR0        0X104   /* Local space register values    */
49 #define PCISH5_ICR_LSR1        0X108   /* Local space register values    */
50 #define PCISH5_ICR_LAR0        0x10c   /* Local address register values  */
51 #define PCISH5_ICR_LAR1        0x110   /* Local address register values  */
52 #define PCISH5_ICR_INTM        0x118   /* Interrupt mask register values                         */
53 #define PCISH5_ICR_AIR         0x11c   /* Interrupt error address information register values    */
54 #define PCISH5_ICR_CIR         0x120   /* Interrupt error command information register values    */
55 #define PCISH5_ICR_AINT        0x130   /* Interrupt error arbiter interrupt register values      */
56 #define PCISH5_ICR_AINTM       0x134   /* Interrupt error arbiter interrupt mask register values */
57 #define PCISH5_ICR_BMIR        0x138   /* Interrupt error info register of bus master values     */
58 #define PCISH5_ICR_PAR         0x1c0   /* Pio address register values                            */
59 #define PCISH5_ICR_MBR         0x1c4   /* Memory space bank register values                      */
60 #define PCISH5_ICR_IOBR        0x1c8   /* I/O space bank register values                         */
61 #define PCISH5_ICR_PINT        0x1cc   /* power management interrupt register values             */
62 #define PCISH5_ICR_PINTM       0x1d0   /* power management interrupt mask register values        */
63 #define PCISH5_ICR_MBMR        0x1d8   /* memory space bank mask register values                 */
64 #define PCISH5_ICR_IOBMR       0x1dc   /* I/O space bank mask register values                    */
67 #define PCISH5_ICR_PDR         0x220   /* Pio data register values                               */