Lines Matching +full:data +full:- +full:lines
10 of SH5-101 cut2 eval chip with Cayman board DDR memory.
19 * Currently the prefetch is 4 lines ahead and the alloco is 2 lines ahead.
20 It seems like the prefetch needs to be at at least 4 lines ahead to get
21 the data into the cache in time, and the allocos contend with outstanding
33 /* Copy 4096 bytes worth of data from r3 to r2.
34 Do prefetches 4 lines ahead.
35 Do alloco 2 lines ahead */
70 bge/u r2, r6, tr2 ! skip prefetch for last 4 lines
71 ldx.q r2, r22, r63 ! prefetch 4 lines hence
74 bge/u r2, r7, tr3 ! skip alloco for last 2 lines
75 alloco r2, 0x40 ! alloc destination line 2 lines ahead