Lines Matching +full:multi +full:- +full:address

1 # SPDX-License-Identifier: GPL-2.0
12 	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
15 	  On other systems (such as the SH-3 and 4) where an MMU exists,
49 	hex "Physical memory start address"
51 	---help---
53 	  map the ROM starting at address zero.  But the processor
56 	  The physical memory (RAM) start address will be automatically
86 	bool "Support 32-bit physical addressing through PMB"
92 	  32-bits through the SH-4A PMB. If this is not set, legacy
93 	  29-bit physical addressing will be used.
119 	  the address space, each with varying latencies. This enables
180 	  This enables 8kB pages as supported by SH-X2 and later MMUs.
186 	  This enables 16kB pages on MMU-less SH systems.
192 	  This enables support for 64kB pages, possible on all SH-4
229 	bool "Multi-core scheduler support"
233 	  Multi-core scheduler support improves the CPU scheduler's decision
234 	  making when dealing with multi-core CPU chips at a cost of slightly
252 	bool "Write-back"
255 	bool "Write-through"
257 	  Selecting this option will configure the caches in write-through
258 	  mode, as opposed to the default write-back configuration.
260 	  Since there's sill some aliasing issues on SH-4, this option will