Lines Matching +full:top +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0
56 #define LEVEL(x) P(LVLNUM, x) macro
62 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
63 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
64 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
65 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
66 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
67 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
68 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
69 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
70 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
71 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
72 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
73 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
74 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
75 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
76 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
77 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
83 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
84 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
85 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
90 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4); in intel_pmu_pebs_data_source_skl()
94 pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); in intel_pmu_pebs_data_source_skl()
95 pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); in intel_pmu_pebs_data_source_skl()
96 pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); in intel_pmu_pebs_data_source_skl()
108 * 1 = stored missed 2nd level TLB in precise_store_data()
111 * otherwise hit 2nd level TLB in precise_store_data()
143 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) in precise_datala_hsw()
145 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) in precise_datala_hsw()
156 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { in precise_datala_hsw()
173 * use the mapping table for bit 0-3 in load_latency_data()
186 * 0 = did not miss 2nd level TLB in load_latency_data()
187 * 1 = missed 2nd level TLB in load_latency_data()
298 * This is a cross-CPU update of the cpu_entry_area, we must shoot down in ds_update_cea()
337 struct debug_store *ds = hwev->ds; in alloc_pebs_buffer()
347 return -ENOMEM; in alloc_pebs_buffer()
357 return -ENOMEM; in alloc_pebs_buffer()
361 hwev->ds_pebs_vaddr = buffer; in alloc_pebs_buffer()
363 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; in alloc_pebs_buffer()
364 ds->pebs_buffer_base = (unsigned long) cea; in alloc_pebs_buffer()
366 ds->pebs_index = ds->pebs_buffer_base; in alloc_pebs_buffer()
368 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max; in alloc_pebs_buffer()
384 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; in release_pebs_buffer()
386 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
387 hwev->ds_pebs_vaddr = NULL; in release_pebs_buffer()
393 struct debug_store *ds = hwev->ds; in alloc_bts_buffer()
403 return -ENOMEM; in alloc_bts_buffer()
405 hwev->ds_bts_vaddr = buffer; in alloc_bts_buffer()
407 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; in alloc_bts_buffer()
408 ds->bts_buffer_base = (unsigned long) cea; in alloc_bts_buffer()
410 ds->bts_index = ds->bts_buffer_base; in alloc_bts_buffer()
412 ds->bts_absolute_maximum = ds->bts_buffer_base + in alloc_bts_buffer()
414 ds->bts_interrupt_threshold = ds->bts_absolute_maximum - in alloc_bts_buffer()
428 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; in release_bts_buffer()
430 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE); in release_bts_buffer()
431 hwev->ds_bts_vaddr = NULL; in release_bts_buffer()
436 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store; in alloc_ds_buffer()
568 if (!cpuc->ds) in intel_pmu_disable_bts()
583 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_bts_buffer()
589 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; in intel_pmu_drain_bts_buffer()
590 struct bts_record *at, *base, *top; in intel_pmu_drain_bts_buffer() local
603 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; in intel_pmu_drain_bts_buffer()
604 top = (struct bts_record *)(unsigned long)ds->bts_index; in intel_pmu_drain_bts_buffer()
606 if (top <= base) in intel_pmu_drain_bts_buffer()
611 ds->bts_index = ds->bts_buffer_base; in intel_pmu_drain_bts_buffer()
613 perf_sample_data_init(&data, 0, event->hw.last_period); in intel_pmu_drain_bts_buffer()
625 for (at = base; at < top; at++) { in intel_pmu_drain_bts_buffer()
631 if (event->attr.exclude_kernel && in intel_pmu_drain_bts_buffer()
632 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
645 (top - base - skip))) in intel_pmu_drain_bts_buffer()
648 for (at = base; at < top; at++) { in intel_pmu_drain_bts_buffer()
650 if (event->attr.exclude_kernel && in intel_pmu_drain_bts_buffer()
651 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
654 data.ip = at->from; in intel_pmu_drain_bts_buffer()
655 data.addr = at->to; in intel_pmu_drain_bts_buffer()
663 event->hw.interrupts++; in intel_pmu_drain_bts_buffer()
664 event->pending_kill = POLL_IN; in intel_pmu_drain_bts_buffer()
856 if (!event->attr.precise_ip) in intel_pebs_constraints()
861 if ((event->hw.config & c->cmask) == c->code) { in intel_pebs_constraints()
862 event->hw.flags |= c->flags; in intel_pebs_constraints()
879 * We need the sched_task callback even for per-cpu events when we use
885 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); in pebs_needs_sched_cb()
898 struct debug_store *ds = cpuc->ds; in pebs_update_threshold()
907 if (cpuc->n_pebs == cpuc->n_large_pebs) { in pebs_update_threshold()
908 threshold = ds->pebs_absolute_maximum - in pebs_update_threshold()
911 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size; in pebs_update_threshold()
914 ds->pebs_interrupt_threshold = threshold; in pebs_update_threshold()
925 bool update = cpuc->n_pebs == 1; in pebs_update_state()
943 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_add()
946 cpuc->n_pebs++; in intel_pmu_pebs_add()
947 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) in intel_pmu_pebs_add()
948 cpuc->n_large_pebs++; in intel_pmu_pebs_add()
950 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); in intel_pmu_pebs_add()
956 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_enable()
957 struct debug_store *ds = cpuc->ds; in intel_pmu_pebs_enable()
959 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_enable()
961 cpuc->pebs_enabled |= 1ULL << hwc->idx; in intel_pmu_pebs_enable()
963 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) in intel_pmu_pebs_enable()
964 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); in intel_pmu_pebs_enable()
965 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) in intel_pmu_pebs_enable()
966 cpuc->pebs_enabled |= 1ULL << 63; in intel_pmu_pebs_enable()
969 * Use auto-reload if possible to save a MSR write in the PMI. in intel_pmu_pebs_enable()
972 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { in intel_pmu_pebs_enable()
973 unsigned int idx = hwc->idx; in intel_pmu_pebs_enable()
976 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED); in intel_pmu_pebs_enable()
977 ds->pebs_event_reset[idx] = in intel_pmu_pebs_enable()
978 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
980 ds->pebs_event_reset[hwc->idx] = 0; in intel_pmu_pebs_enable()
987 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_del()
990 cpuc->n_pebs--; in intel_pmu_pebs_del()
991 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) in intel_pmu_pebs_del()
992 cpuc->n_large_pebs--; in intel_pmu_pebs_del()
994 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); in intel_pmu_pebs_del()
1000 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_disable()
1002 if (cpuc->n_pebs == cpuc->n_large_pebs) in intel_pmu_pebs_disable()
1005 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); in intel_pmu_pebs_disable()
1007 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) in intel_pmu_pebs_disable()
1008 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); in intel_pmu_pebs_disable()
1009 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) in intel_pmu_pebs_disable()
1010 cpuc->pebs_enabled &= ~(1ULL << 63); in intel_pmu_pebs_disable()
1012 if (cpuc->enabled) in intel_pmu_pebs_disable()
1013 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_disable()
1015 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_disable()
1022 if (cpuc->pebs_enabled) in intel_pmu_pebs_enable_all()
1023 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_enable_all()
1030 if (cpuc->pebs_enabled) in intel_pmu_pebs_disable_all()
1037 unsigned long from = cpuc->lbr_entries[0].from; in intel_pmu_pebs_fixup_ip()
1038 unsigned long old_to, to = cpuc->lbr_entries[0].to; in intel_pmu_pebs_fixup_ip()
1039 unsigned long ip = regs->ip; in intel_pmu_pebs_fixup_ip()
1053 if (!cpuc->lbr_stack.nr || !from || !to) in intel_pmu_pebs_fixup_ip()
1066 if ((ip - to) > PEBS_FIXUP_SIZE) in intel_pmu_pebs_fixup_ip()
1077 size = ip - to; in intel_pmu_pebs_fixup_ip()
1113 size -= insn.length; in intel_pmu_pebs_fixup_ip()
1130 if (pebs->tsx_tuning) { in intel_hsw_weight()
1131 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning }; in intel_hsw_weight()
1139 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; in intel_hsw_transaction()
1142 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1)) in intel_hsw_transaction()
1143 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; in intel_hsw_transaction()
1164 int fl = event->hw.flags; in setup_pebs_sample_data()
1169 sample_type = event->attr.sample_type; in setup_pebs_sample_data()
1175 perf_sample_data_init(data, 0, event->hw.last_period); in setup_pebs_sample_data()
1177 data->period = event->hw.last_period; in setup_pebs_sample_data()
1180 * Use latency for weight (only avail with PEBS-LL) in setup_pebs_sample_data()
1183 data->weight = pebs->lat; in setup_pebs_sample_data()
1191 val = load_latency_data(pebs->dse); in setup_pebs_sample_data()
1193 val = precise_datala_hsw(event, pebs->dse); in setup_pebs_sample_data()
1195 val = precise_store_data(pebs->dse); in setup_pebs_sample_data()
1196 data->data_src.val = val; in setup_pebs_sample_data()
1206 data->callchain = perf_callchain(event, iregs); in setup_pebs_sample_data()
1222 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT; in setup_pebs_sample_data()
1225 regs->ax = pebs->ax; in setup_pebs_sample_data()
1226 regs->bx = pebs->bx; in setup_pebs_sample_data()
1227 regs->cx = pebs->cx; in setup_pebs_sample_data()
1228 regs->dx = pebs->dx; in setup_pebs_sample_data()
1229 regs->si = pebs->si; in setup_pebs_sample_data()
1230 regs->di = pebs->di; in setup_pebs_sample_data()
1232 regs->bp = pebs->bp; in setup_pebs_sample_data()
1233 regs->sp = pebs->sp; in setup_pebs_sample_data()
1236 regs->r8 = pebs->r8; in setup_pebs_sample_data()
1237 regs->r9 = pebs->r9; in setup_pebs_sample_data()
1238 regs->r10 = pebs->r10; in setup_pebs_sample_data()
1239 regs->r11 = pebs->r11; in setup_pebs_sample_data()
1240 regs->r12 = pebs->r12; in setup_pebs_sample_data()
1241 regs->r13 = pebs->r13; in setup_pebs_sample_data()
1242 regs->r14 = pebs->r14; in setup_pebs_sample_data()
1243 regs->r15 = pebs->r15; in setup_pebs_sample_data()
1247 if (event->attr.precise_ip > 1) { in setup_pebs_sample_data()
1250 * (real IP) which fixes the off-by-1 skid in hardware. in setup_pebs_sample_data()
1254 set_linear_ip(regs, pebs->real_ip); in setup_pebs_sample_data()
1255 regs->flags |= PERF_EFLAGS_EXACT; in setup_pebs_sample_data()
1257 /* Otherwise, use PEBS off-by-1 IP: */ in setup_pebs_sample_data()
1258 set_linear_ip(regs, pebs->ip); in setup_pebs_sample_data()
1261 * With precise_ip >= 2, try to fix up the off-by-1 IP in setup_pebs_sample_data()
1263 * corrects regs->ip and calls set_linear_ip() on regs: in setup_pebs_sample_data()
1266 regs->flags |= PERF_EFLAGS_EXACT; in setup_pebs_sample_data()
1270 * When precise_ip == 1, return the PEBS off-by-1 IP, in setup_pebs_sample_data()
1273 set_linear_ip(regs, pebs->ip); in setup_pebs_sample_data()
1279 data->addr = pebs->dla; in setup_pebs_sample_data()
1284 data->weight = intel_hsw_weight(pebs); in setup_pebs_sample_data()
1287 data->txn = intel_hsw_transaction(pebs); in setup_pebs_sample_data()
1297 event->attr.use_clockid == 0) in setup_pebs_sample_data()
1298 data->time = native_sched_clock_from_tsc(pebs->tsc); in setup_pebs_sample_data()
1301 data->br_stack = &cpuc->lbr_stack; in setup_pebs_sample_data()
1305 get_next_pebs_record_by_bit(void *base, void *top, int bit) in get_next_pebs_record_by_bit() argument
1321 for (at = base; at < top; at += x86_pmu.pebs_record_size) { in get_next_pebs_record_by_bit()
1324 if (test_bit(bit, (unsigned long *)&p->status)) { in get_next_pebs_record_by_bit()
1329 if (p->status == (1 << bit)) in get_next_pebs_record_by_bit()
1332 /* clear non-PEBS bit and re-check */ in get_next_pebs_record_by_bit()
1333 pebs_status = p->status & cpuc->pebs_enabled; in get_next_pebs_record_by_bit()
1344 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)); in intel_pmu_auto_reload_read()
1346 perf_pmu_disable(event->pmu); in intel_pmu_auto_reload_read()
1348 perf_pmu_enable(event->pmu); in intel_pmu_auto_reload_read()
1352 * Special variant of intel_pmu_save_and_restart() for auto-reload.
1357 struct hw_perf_event *hwc = &event->hw; in intel_pmu_save_and_restart_reload()
1358 int shift = 64 - x86_pmu.cntval_bits; in intel_pmu_save_and_restart_reload()
1359 u64 period = hwc->sample_period; in intel_pmu_save_and_restart_reload()
1370 prev_raw_count = local64_read(&hwc->prev_count); in intel_pmu_save_and_restart_reload()
1371 rdpmcl(hwc->event_base_rdpmc, new_raw_count); in intel_pmu_save_and_restart_reload()
1372 local64_set(&hwc->prev_count, new_raw_count); in intel_pmu_save_and_restart_reload()
1378 * [-period, 0] in intel_pmu_save_and_restart_reload()
1382 * A) value2 - value1; in intel_pmu_save_and_restart_reload()
1385 * B) (0 - value1) + (value2 - (-period)); in intel_pmu_save_and_restart_reload()
1388 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period)); in intel_pmu_save_and_restart_reload()
1392 * discrete interval, where the first term is to the top of the in intel_pmu_save_and_restart_reload()
1399 * value2 - value1 + n * period in intel_pmu_save_and_restart_reload()
1403 local64_add(new - old + count * period, &event->count); in intel_pmu_save_and_restart_reload()
1405 local64_set(&hwc->period_left, -new); in intel_pmu_save_and_restart_reload()
1414 void *base, void *top, in __intel_pmu_pebs_event() argument
1417 struct hw_perf_event *hwc = &event->hw; in __intel_pmu_pebs_event()
1420 void *at = get_next_pebs_record_by_bit(base, top, bit); in __intel_pmu_pebs_event()
1422 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { in __intel_pmu_pebs_event()
1424 * Now, auto-reload is only enabled in fixed period mode. in __intel_pmu_pebs_event()
1425 * The reload value is always hwc->sample_period. in __intel_pmu_pebs_event()
1426 * May need to change it, if auto-reload is enabled in in __intel_pmu_pebs_event()
1437 at = get_next_pebs_record_by_bit(at, top, bit); in __intel_pmu_pebs_event()
1438 count--; in __intel_pmu_pebs_event()
1457 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_core()
1458 struct perf_event *event = cpuc->events[0]; /* PMC0 only */ in intel_pmu_drain_pebs_core()
1459 struct pebs_record_core *at, *top; in intel_pmu_drain_pebs_core() local
1465 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_core()
1466 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_core()
1471 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_core()
1473 if (!test_bit(0, cpuc->active_mask)) in intel_pmu_drain_pebs_core()
1478 if (!event->attr.precise_ip) in intel_pmu_drain_pebs_core()
1481 n = top - at; in intel_pmu_drain_pebs_core()
1483 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) in intel_pmu_drain_pebs_core()
1488 __intel_pmu_pebs_event(event, iregs, at, top, 0, n); in intel_pmu_drain_pebs_core()
1494 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_nhm()
1496 void *base, *at, *top; in intel_pmu_drain_pebs_nhm() local
1505 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_nhm()
1506 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_nhm()
1508 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_nhm()
1510 mask = (1ULL << x86_pmu.max_pebs_events) - 1; in intel_pmu_drain_pebs_nhm()
1513 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED; in intel_pmu_drain_pebs_nhm()
1517 if (unlikely(base >= top)) { in intel_pmu_drain_pebs_nhm()
1520 * for auto-reload event in pmu::read(). There are no in intel_pmu_drain_pebs_nhm()
1523 * update the event->count for this case. in intel_pmu_drain_pebs_nhm()
1525 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, in intel_pmu_drain_pebs_nhm()
1527 event = cpuc->events[bit]; in intel_pmu_drain_pebs_nhm()
1528 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) in intel_pmu_drain_pebs_nhm()
1534 for (at = base; at < top; at += x86_pmu.pebs_record_size) { in intel_pmu_drain_pebs_nhm()
1538 pebs_status = p->status & cpuc->pebs_enabled; in intel_pmu_drain_pebs_nhm()
1558 if (!pebs_status && cpuc->pebs_enabled && in intel_pmu_drain_pebs_nhm()
1559 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) in intel_pmu_drain_pebs_nhm()
1560 pebs_status = p->status = cpuc->pebs_enabled; in intel_pmu_drain_pebs_nhm()
1572 * If these events include one PEBS and multiple non-PEBS in intel_pmu_drain_pebs_nhm()
1582 if (p->status != (1ULL << bit)) { in intel_pmu_drain_pebs_nhm()
1596 event = cpuc->events[bit]; in intel_pmu_drain_pebs_nhm()
1600 if (WARN_ON_ONCE(!event->attr.precise_ip)) in intel_pmu_drain_pebs_nhm()
1613 top, bit, counts[bit]); in intel_pmu_drain_pebs_nhm()
1634 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; in intel_ds_init()