Lines Matching +full:0 +full:x8000000a
94 u64 avic_backing_page; /* Offset 0xe0 */
95 u8 reserved_6[8]; /* Offset 0xe8 */
96 u64 avic_logical_id; /* Offset 0xf0 */
97 u64 avic_physical_id; /* Offset 0xf8 */
102 #define TLB_CONTROL_DO_NOTHING 0
107 #define V_TPR_MASK 0x0f
116 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
132 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
148 #define SVM_VM_CR_VALID_MASK 0x001fULL
149 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
150 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
152 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
212 #define SVM_CPUID_FUNC 0x8000000a
224 #define SVM_SELECTOR_TYPE_MASK (0xf)
237 #define INTERCEPT_CR0_READ 0
241 #define INTERCEPT_CR0_WRITE (16 + 0)
246 #define INTERCEPT_DR0_READ 0
254 #define INTERCEPT_DR0_WRITE (16 + 0)
263 #define SVM_EVTINJ_VEC_MASK 0xff
268 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
291 #define SVM_EXITINFO_REG_MASK 0x0F
295 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
296 #define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
297 #define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
298 #define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
299 #define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
300 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"