Lines Matching +full:0 +full:x802000
37 * the size of the region by writing ~0 to a base address register
42 * ~0 to a base address register.
45 static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
46 0x0, 0x0, 0x0, 0x0,
47 0x0, 0x0, 0x0, 0x0,
49 0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */
50 0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */
51 0x0, 0x0, 0x0, 0x28100b,
52 0x0, 0x0, 0x0, 0x0,
53 0x0, 0x0, 0x0, 0x0,
54 0x0, 0x0, 0x0, 0x0,
55 0x0, 0x0, 0x0, 0x0,
58 static const uint32_t gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
59 0xfffffffd, 0x0, 0x0, 0x0,
60 0x0, 0x0, 0x0, 0x0,
62 0x28100b, 0x2200005, 0x6000021, 0x80f808, /* NSC Vendor ID */
63 0xac1d, 0x0, 0x0, 0x0, /* I/O BAR - base of virtual registers */
64 0x0, 0x0, 0x0, 0x28100b,
65 0x0, 0x0, 0x0, 0x0,
66 0x0, 0x0, 0x0, 0x0,
67 0x0, 0x0, 0x0, 0x0,
68 0x0, 0x0, 0x0, 0x0,
72 0xff000008, 0xffffc000, 0xffffc000, 0xffffc000,
73 0xffffc000, 0x0, 0x0, 0x0,
75 0x20811022, 0x2200003, 0x3000000, 0x0, /* AMD Vendor ID */
76 0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000, /* FB, GP, VG, DF */
77 0xfe00c000, 0x0, 0x0, 0x30100b, /* VIP */
78 0x0, 0x0, 0x0, 0x10e, /* INTA, IRQ14 for graphics accel */
79 0x0, 0x0, 0x0, 0x0,
80 0x3d0, 0x3c0, 0xa0000, 0x0, /* VG IO, VG IO, EGA FB, MONO FB */
81 0x0, 0x0, 0x0, 0x0,
85 0xff800008, 0xffffc000, 0xffffc000, 0xffffc000,
86 0x0, 0x0, 0x0, 0x0,
88 0x30100b, 0x2200003, 0x3000000, 0x0, /* NSC Vendor ID */
89 0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000, /* FB, GP, VG, DF */
90 0x0, 0x0, 0x0, 0x30100b,
91 0x0, 0x0, 0x0, 0x0,
92 0x0, 0x0, 0x0, 0x0,
93 0x3d0, 0x3c0, 0xa0000, 0x0, /* VG IO, VG IO, EGA FB, MONO FB */
94 0x0, 0x0, 0x0, 0x0,
97 static const uint32_t aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */
98 0xffffc000, 0x0, 0x0, 0x0,
99 0x0, 0x0, 0x0, 0x0,
101 0x20821022, 0x2a00006, 0x10100000, 0x8, /* NSC Vendor ID */
102 0xfe010000, 0x0, 0x0, 0x0, /* AES registers */
103 0x0, 0x0, 0x0, 0x20821022,
104 0x0, 0x0, 0x0, 0x0,
105 0x0, 0x0, 0x0, 0x0,
106 0x0, 0x0, 0x0, 0x0,
107 0x0, 0x0, 0x0, 0x0,
111 static const uint32_t isa_hdr[] = { /* dev f function 0 - devfn = 78 */
112 0xfffffff9, 0xffffff01, 0xffffffc1, 0xffffffe1,
113 0xffffff81, 0xffffffc1, 0x0, 0x0,
115 0x20901022, 0x2a00049, 0x6010003, 0x802000,
116 0x18b1, 0x1001, 0x1801, 0x1881, /* SMB-8 GPIO-256 MFGPT-64 IRQ-32 */
117 0x1401, 0x1841, 0x0, 0x20901022, /* PMS-128 ACPI-64 */
118 0x0, 0x0, 0x0, 0x0,
119 0x0, 0x0, 0x0, 0x0,
120 0x0, 0x0, 0x0, 0xaa5b, /* IRQ steering */
121 0x0, 0x0, 0x0, 0x0,
125 0xffffff81, 0x0, 0x0, 0x0,
126 0x0, 0x0, 0x0, 0x0,
128 0x20931022, 0x2a00041, 0x4010001, 0x0,
129 0x1481, 0x0, 0x0, 0x0, /* I/O BAR-128 */
130 0x0, 0x0, 0x0, 0x20931022,
131 0x0, 0x0, 0x0, 0x205, /* IntB, IRQ5 */
132 0x0, 0x0, 0x0, 0x0,
133 0x0, 0x0, 0x0, 0x0,
134 0x0, 0x0, 0x0, 0x0,
138 0xfffff000, 0x0, 0x0, 0x0,
139 0x0, 0x0, 0x0, 0x0,
141 0x20941022, 0x2300006, 0xc031002, 0x0,
142 0xfe01a000, 0x0, 0x0, 0x0, /* MEMBAR-1000 */
143 0x0, 0x0, 0x0, 0x20941022,
144 0x0, 0x40, 0x0, 0x40a, /* CapPtr INT-D, IRQA */
145 0xc8020001, 0x0, 0x0, 0x0, /* Capabilities - 40 is R/O,
147 0x0, 0x0, 0x0, 0x0,
148 0x0, 0x0, 0x0, 0x0,
152 0xfffff000, 0x0, 0x0, 0x0,
153 0x0, 0x0, 0x0, 0x0,
155 0x20951022, 0x2300006, 0xc032002, 0x0,
156 0xfe01b000, 0x0, 0x0, 0x0, /* MEMBAR-1000 */
157 0x0, 0x0, 0x0, 0x20951022,
158 0x0, 0x40, 0x0, 0x40a, /* CapPtr INT-D, IRQA */
159 0xc8020001, 0x0, 0x0, 0x0, /* Capabilities - 40 is R/O, 44 is
161 #if 0
162 0x1, 0x40080000, 0x0, 0x0, /* EECP - see EHCI spec section 2.1.7 */
164 0x01000001, 0x0, 0x0, 0x0, /* EECP - see EHCI spec section 2.1.7 */
165 0x2020, 0x0, 0x0, 0x0, /* (EHCI page 8) 60 SBRN (R/O),
169 static uint32_t ff_loc = ~0;
171 static int bar_probing; /* Set after a write of ~0 to a BAR */
174 #define NB_SLOT 0x1 /* Northbridge - GX chip - Device 1 */
175 #define SB_SLOT 0xf /* Southbridge - CS5536 chip - Device F */
189 * 0x20 bytes of size masks, followed by 0x70 bytes of header data. in hdr_addr()
191 * to access the header data, so we add 0x20 to the reg offset, in hdr_addr()
194 * the BAR, so we subtract 0x10 (the config header offset for in hdr_addr()
198 addr = (uint32_t)hdr + reg + (bar_probing ? -0x10 : 0x20); in hdr_addr()
200 bar_probing = 0; in hdr_addr()
216 * No device has config registers past 0x70, so we save table space in pci_olpc_read()
219 if (reg >= 0x70) in pci_olpc_read()
223 case 0x8: in pci_olpc_read()
226 case 0x9: in pci_olpc_read()
229 case 0xa: in pci_olpc_read()
232 case 0x78: in pci_olpc_read()
235 case 0x7b: in pci_olpc_read()
238 case 0x7c: in pci_olpc_read()
241 case 0x7d: in pci_olpc_read()
263 return 0; in pci_olpc_read()
279 * (i.e. writing ~0 to a BAR), we remember it and arrange to return in pci_olpc_write()
285 if ((reg >= 0x10) && (reg < 0x2c)) { in pci_olpc_write()
287 if (value == ~0) in pci_olpc_write()
296 (reg != PCI_CACHE_LINE_SIZE) && (reg != 0x44)) in pci_olpc_write()
301 return 0; in pci_olpc_write()
314 return 0; in pci_olpc_init()