Lines Matching +full:host +full:- +full:port
2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * --> Develop a low-power-consumption strategy, and implement it.
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
44 * 80x1-B2 errata PCI#11:
47 * should be careful to insert those cards only onto PCI-X bus #0,
60 #include <linux/dma-mapping.h>
108 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
110 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
116 * Per-chip ("all ports") interrupt coalescing feature.
146 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
157 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
160 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
161 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
163 /* Host Flags */
164 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
177 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
178 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
179 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
185 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
186 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
216 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
222 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
227 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
228 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
229 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
230 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
242 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
243 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
244 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
250 DMA_IRQ = (1 << 0), /* shift by port # */
252 DEV_IRQ = (1 << 8), /* shift by port # */
255 * Per-HC (Host-Controller) interrupt coalescing feature.
279 LTMODE = 0x30c, /* requires read-after-write */
285 PHY_MODE4 = 0x314, /* requires read-after-write */
297 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
317 /* Port registers */
324 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
325 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
335 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
336 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
410 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
428 /* Host private flags (hp_flags) */
438 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
443 /* Port private flags (pp_flags) */
451 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
452 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
453 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
454 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
455 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
462 * we need on /length/ in mv_fill-sg().
518 * We keep a local cache of a few frequently accessed port
520 * when switching between EDMA and non-EDMA modes.
569 * all the clock operations become no-ops (see clk.h).
581 * alignment for hardware-accessed data structures,
591 unsigned int port);
598 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
618 unsigned int port);
625 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
628 unsigned int port);
643 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
645 void __iomem *mmio, unsigned int port);
646 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
683 .can_queue = MV_MAX_Q_DEPTH - 1,
875 static inline unsigned int mv_hc_from_port(unsigned int port) in mv_hc_from_port() argument
877 return port >> MV_PORT_HC_SHIFT; in mv_hc_from_port()
880 static inline unsigned int mv_hardport_from_port(unsigned int port) in mv_hardport_from_port() argument
882 return port & MV_PORT_MASK; in mv_hardport_from_port()
887 * This is hot-path stuff, so not a function.
890 * port is the sole input, in range 0..7.
894 * Note that port and hardport may be the same variable in some cases.
896 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ argument
898 shift = mv_hc_from_port(port) * HC_SHIFT; \
899 hardport = mv_hardport_from_port(port); \
909 unsigned int port) in mv_hc_base_from_port() argument
911 return mv_hc_base(base, mv_hc_from_port(port)); in mv_hc_base_from_port()
914 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) in mv_port_base() argument
916 return mv_hc_base_from_port(base, port) + in mv_port_base()
918 (mv_hardport_from_port(port) * MV_PORT_REG_SZ); in mv_port_base()
921 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) in mv5_phy_base() argument
923 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); in mv5_phy_base()
924 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; in mv5_phy_base()
929 static inline void __iomem *mv_host_base(struct ata_host *host) in mv_host_base() argument
931 struct mv_host_priv *hpriv = host->private_data; in mv_host_base()
932 return hpriv->base; in mv_host_base()
937 return mv_port_base(mv_host_base(ap->host), ap->port_no); in mv_ap_base()
946 * mv_save_cached_regs - (re-)initialize cached port registers
947 * @ap: the port whose registers we are caching
949 * Initialize the local cache of port registers,
958 struct mv_port_priv *pp = ap->private_data; in mv_save_cached_regs()
960 pp->cached.fiscfg = readl(port_mmio + FISCFG); in mv_save_cached_regs()
961 pp->cached.ltmode = readl(port_mmio + LTMODE); in mv_save_cached_regs()
962 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); in mv_save_cached_regs()
963 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); in mv_save_cached_regs()
967 * mv_write_cached_reg - write to a cached port register
981 * Workaround for 88SX60x1-B2 FEr SATA#13: in mv_write_cached_reg()
982 * Read-after-write is needed to prevent generating 64-bit in mv_write_cached_reg()
987 * +1 usec read-after-write delay for unaffected registers. in mv_write_cached_reg()
1010 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
1011 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_set_edma_ptrs()
1013 WARN_ON(pp->crqb_dma & 0x3ff); in mv_set_edma_ptrs()
1014 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); in mv_set_edma_ptrs()
1015 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
1022 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
1023 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; in mv_set_edma_ptrs()
1025 WARN_ON(pp->crpb_dma & 0xff); in mv_set_edma_ptrs()
1026 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); in mv_set_edma_ptrs()
1028 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
1037 * and the corresponding individual port DONE_IRQ bits. in mv_write_main_irq_mask()
1046 writelfl(mask, hpriv->main_irq_mask_addr); in mv_write_main_irq_mask()
1049 static void mv_set_main_irq_mask(struct ata_host *host, in mv_set_main_irq_mask() argument
1052 struct mv_host_priv *hpriv = host->private_data; in mv_set_main_irq_mask()
1055 old_mask = hpriv->main_irq_mask; in mv_set_main_irq_mask()
1058 hpriv->main_irq_mask = new_mask; in mv_set_main_irq_mask()
1066 unsigned int shift, hardport, port = ap->port_no; in mv_enable_port_irqs() local
1069 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); in mv_enable_port_irqs()
1073 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); in mv_enable_port_irqs()
1080 struct mv_host_priv *hpriv = ap->host->private_data; in mv_clear_and_enable_port_irqs()
1081 int hardport = mv_hardport_from_port(ap->port_no); in mv_clear_and_enable_port_irqs()
1083 mv_host_base(ap->host), ap->port_no); in mv_clear_and_enable_port_irqs()
1100 static void mv_set_irq_coalescing(struct ata_host *host, in mv_set_irq_coalescing() argument
1103 struct mv_host_priv *hpriv = host->private_data; in mv_set_irq_coalescing()
1104 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_set_irq_coalescing()
1107 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; in mv_set_irq_coalescing()
1123 spin_lock_irqsave(&host->lock, flags); in mv_set_irq_coalescing()
1124 mv_set_main_irq_mask(host, coal_disable, 0); in mv_set_irq_coalescing()
1128 * GEN_II/GEN_IIE with dual host controllers: in mv_set_irq_coalescing()
1158 mv_set_main_irq_mask(host, 0, coal_enable); in mv_set_irq_coalescing()
1159 spin_unlock_irqrestore(&host->lock, flags); in mv_set_irq_coalescing()
1163 * mv_start_edma - Enable eDMA engine
1164 * @base: port base address
1165 * @pp: port private data
1178 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { in mv_start_edma()
1179 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); in mv_start_edma()
1183 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { in mv_start_edma()
1184 struct mv_host_priv *hpriv = ap->host->private_data; in mv_start_edma()
1192 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; in mv_start_edma()
1207 * with two drives in-use. So we use the 15msec value above in mv_wait_for_edma_empty_idle()
1220 * mv_stop_edma_engine - Disable eDMA engine
1234 for (i = 10000; i > 0; i--) { in mv_stop_edma_engine()
1240 return -EIO; in mv_stop_edma_engine()
1246 struct mv_port_priv *pp = ap->private_data; in mv_stop_edma()
1249 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_stop_edma()
1251 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_stop_edma()
1255 err = -EIO; in mv_stop_edma()
1293 static void mv_dump_all_regs(void __iomem *mmio_base, int port, in mv_dump_all_regs() argument
1298 port >> MV_PORT_HC_SHIFT); in mv_dump_all_regs()
1302 if (0 > port) { in mv_dump_all_regs()
1304 num_ports = 8; /* shld be benign for 4 port devs */ in mv_dump_all_regs()
1307 start_hc = port >> MV_PORT_HC_SHIFT; in mv_dump_all_regs()
1308 start_port = port; in mv_dump_all_regs()
1311 DPRINTK("All registers for port(s) %u-%u:\n", start_port, in mv_dump_all_regs()
1312 num_ports > 1 ? num_ports - 1 : start_port); in mv_dump_all_regs()
1330 DPRINTK("EDMA regs (port %i):\n", p); in mv_dump_all_regs()
1332 DPRINTK("SATA regs (port %i):\n", p); in mv_dump_all_regs()
1363 *val = readl(mv_ap_base(link->ap) + ofs); in mv_scr_read()
1366 return -EINVAL; in mv_scr_read()
1374 void __iomem *addr = mv_ap_base(link->ap) + ofs; in mv_scr_write()
1375 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv_scr_write()
1393 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { in mv_scr_write()
1395 mv_ap_base(link->ap) + LP_PHY_CTL; in mv_scr_write()
1415 return -EINVAL; in mv_scr_write()
1421 * Deal with Gen-II ("mv6") hardware quirks/restrictions: in mv6_dev_config()
1423 * Gen-II does not support NCQ over a port multiplier in mv6_dev_config()
1424 * (no FIS-based switching). in mv6_dev_config()
1426 if (adev->flags & ATA_DFLAG_NCQ) { in mv6_dev_config()
1427 if (sata_pmp_attached(adev->link->ap)) { in mv6_dev_config()
1428 adev->flags &= ~ATA_DFLAG_NCQ; in mv6_dev_config()
1430 "NCQ disabled for command-based switching\n"); in mv6_dev_config()
1437 struct ata_link *link = qc->dev->link; in mv_qc_defer()
1438 struct ata_port *ap = link->ap; in mv_qc_defer()
1439 struct mv_port_priv *pp = ap->private_data; in mv_qc_defer()
1443 * for NCQ and/or FIS-based switching. in mv_qc_defer()
1445 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_qc_defer()
1451 * or a non-NCQ command in NCQ mode. in mv_qc_defer()
1456 if (unlikely(ap->excl_link)) { in mv_qc_defer()
1457 if (link == ap->excl_link) { in mv_qc_defer()
1458 if (ap->nr_active_links) in mv_qc_defer()
1460 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; in mv_qc_defer()
1467 * If the port is completely idle, then allow the new qc. in mv_qc_defer()
1469 if (ap->nr_active_links == 0) in mv_qc_defer()
1473 * The port is operating in host queuing mode (EDMA) with NCQ in mv_qc_defer()
1478 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && in mv_qc_defer()
1479 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { in mv_qc_defer()
1480 if (ata_is_ncq(qc->tf.protocol)) in mv_qc_defer()
1483 ap->excl_link = link; in mv_qc_defer()
1493 struct mv_port_priv *pp = ap->private_data; in mv_config_fbs()
1496 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; in mv_config_fbs()
1497 u32 ltmode, *old_ltmode = &pp->cached.ltmode; in mv_config_fbs()
1498 u32 haltcond, *old_haltcond = &pp->cached.haltcond; in mv_config_fbs()
1522 struct mv_host_priv *hpriv = ap->host->private_data; in mv_60x1_errata_sata25()
1526 old = readl(hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1532 writel(new, hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1536 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1537 * @ap: Port being initialized
1541 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1549 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_enable_iie()
1550 u32 new, *old = &pp->cached.unknown_rsvd; in mv_bmdma_enable_iie()
1566 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1575 struct ata_host *host = ap->host; in mv_soc_led_blink_enable() local
1576 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_enable()
1580 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) in mv_soc_led_blink_enable()
1582 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_enable()
1583 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_enable()
1590 struct ata_host *host = ap->host; in mv_soc_led_blink_disable() local
1591 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_disable()
1594 unsigned int port; in mv_soc_led_blink_disable() local
1596 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) in mv_soc_led_blink_disable()
1599 /* disable led-blink only if no ports are using NCQ */ in mv_soc_led_blink_disable()
1600 for (port = 0; port < hpriv->n_ports; port++) { in mv_soc_led_blink_disable()
1601 struct ata_port *this_ap = host->ports[port]; in mv_soc_led_blink_disable()
1602 struct mv_port_priv *pp = this_ap->private_data; in mv_soc_led_blink_disable()
1604 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_soc_led_blink_disable()
1608 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_disable()
1609 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_disable()
1617 struct mv_port_priv *pp = ap->private_data; in mv_edma_cfg()
1618 struct mv_host_priv *hpriv = ap->host->private_data; in mv_edma_cfg()
1621 /* set up non-NCQ EDMA configuration */ in mv_edma_cfg()
1623 pp->pp_flags &= in mv_edma_cfg()
1638 * The chip can use FBS with non-NCQ, if we allow it, in mv_edma_cfg()
1641 * So disallow non-NCQ FBS for now. in mv_edma_cfg()
1648 pp->pp_flags |= MV_PP_FLAG_FBS_EN; in mv_edma_cfg()
1649 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ in mv_edma_cfg()
1654 cfg |= (1 << 22); /* enab 4-entry host queue cache */ in mv_edma_cfg()
1658 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) in mv_edma_cfg()
1659 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ in mv_edma_cfg()
1672 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; in mv_edma_cfg()
1680 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_free_dma_mem()
1681 struct mv_port_priv *pp = ap->private_data; in mv_port_free_dma_mem()
1684 if (pp->crqb) { in mv_port_free_dma_mem()
1685 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); in mv_port_free_dma_mem()
1686 pp->crqb = NULL; in mv_port_free_dma_mem()
1688 if (pp->crpb) { in mv_port_free_dma_mem()
1689 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); in mv_port_free_dma_mem()
1690 pp->crpb = NULL; in mv_port_free_dma_mem()
1697 if (pp->sg_tbl[tag]) { in mv_port_free_dma_mem()
1699 dma_pool_free(hpriv->sg_tbl_pool, in mv_port_free_dma_mem()
1700 pp->sg_tbl[tag], in mv_port_free_dma_mem()
1701 pp->sg_tbl_dma[tag]); in mv_port_free_dma_mem()
1702 pp->sg_tbl[tag] = NULL; in mv_port_free_dma_mem()
1708 * mv_port_start - Port specific init/start routine.
1711 * Allocate and point to DMA memory, init port private memory,
1719 struct device *dev = ap->host->dev; in mv_port_start()
1720 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_start()
1727 return -ENOMEM; in mv_port_start()
1728 ap->private_data = pp; in mv_port_start()
1730 pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); in mv_port_start()
1731 if (!pp->crqb) in mv_port_start()
1732 return -ENOMEM; in mv_port_start()
1734 pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); in mv_port_start()
1735 if (!pp->crpb) in mv_port_start()
1739 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) in mv_port_start()
1740 ap->flags |= ATA_FLAG_AN; in mv_port_start()
1747 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, in mv_port_start()
1748 GFP_KERNEL, &pp->sg_tbl_dma[tag]); in mv_port_start()
1749 if (!pp->sg_tbl[tag]) in mv_port_start()
1752 pp->sg_tbl[tag] = pp->sg_tbl[0]; in mv_port_start()
1753 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; in mv_port_start()
1757 spin_lock_irqsave(ap->lock, flags); in mv_port_start()
1760 spin_unlock_irqrestore(ap->lock, flags); in mv_port_start()
1766 return -ENOMEM; in mv_port_start()
1770 * mv_port_stop - Port specific cleanup/stop routine.
1773 * Stop DMA, cleanup port memory.
1776 * This routine uses the host lock to protect the DMA stop.
1782 spin_lock_irqsave(ap->lock, flags); in mv_port_stop()
1785 spin_unlock_irqrestore(ap->lock, flags); in mv_port_stop()
1790 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1800 struct mv_port_priv *pp = qc->ap->private_data; in mv_fill_sg()
1805 mv_sg = pp->sg_tbl[qc->hw_tag]; in mv_fill_sg()
1806 for_each_sg(qc->sg, sg, qc->n_elem, si) { in mv_fill_sg()
1815 len = 0x10000 - offset; in mv_fill_sg()
1817 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); in mv_fill_sg()
1818 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); in mv_fill_sg()
1819 mv_sg->flags_size = cpu_to_le32(len & 0xffff); in mv_fill_sg()
1820 mv_sg->reserved = 0; in mv_fill_sg()
1822 sg_len -= len; in mv_fill_sg()
1831 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); in mv_fill_sg()
1843 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1844 * @ap: Port associated with this ATA transaction.
1848 * after libata-sff handles the bmdma interrupts.
1856 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1868 struct scsi_cmnd *scmd = qc->scsicmd; in mv_check_atapi_dma()
1871 switch (scmd->cmnd[0]) { in mv_check_atapi_dma()
1884 return -EOPNOTSUPP; /* use PIO instead */ in mv_check_atapi_dma()
1888 * mv_bmdma_setup - Set up BMDMA transaction
1896 struct ata_port *ap = qc->ap; in mv_bmdma_setup()
1898 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_setup()
1906 writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16, in mv_bmdma_setup()
1908 writelfl(pp->sg_tbl_dma[qc->hw_tag], in mv_bmdma_setup()
1912 ap->ops->sff_exec_command(ap, &qc->tf); in mv_bmdma_setup()
1916 * mv_bmdma_start - Start a BMDMA transaction
1924 struct ata_port *ap = qc->ap; in mv_bmdma_start()
1926 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); in mv_bmdma_start()
1929 /* start host DMA transaction */ in mv_bmdma_start()
1934 * mv_bmdma_stop - Stop BMDMA transfer
1953 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ in mv_bmdma_stop_ap()
1960 mv_bmdma_stop_ap(qc->ap); in mv_bmdma_stop()
1964 * mv_bmdma_status - Read BMDMA status
1965 * @ap: port for which to retrieve DMA status.
1994 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) in mv_bmdma_status()
2004 struct ata_taskfile *tf = &qc->tf; in mv_rw_multi_errata_sata24()
2018 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { in mv_rw_multi_errata_sata24()
2019 if (qc->dev->multi_count > 7) { in mv_rw_multi_errata_sata24()
2020 switch (tf->command) { in mv_rw_multi_errata_sata24()
2022 tf->command = ATA_CMD_PIO_WRITE; in mv_rw_multi_errata_sata24()
2025 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ in mv_rw_multi_errata_sata24()
2028 tf->command = ATA_CMD_PIO_WRITE_EXT; in mv_rw_multi_errata_sata24()
2036 * mv_qc_prep - Host specific command preparation.
2049 struct ata_port *ap = qc->ap; in mv_qc_prep()
2050 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep()
2052 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep()
2056 switch (tf->protocol) { in mv_qc_prep()
2058 if (tf->command == ATA_CMD_DSM) in mv_qc_prep()
2060 /* fall-thru */ in mv_qc_prep()
2072 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep()
2074 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep()
2075 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep()
2076 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep()
2079 in_index = pp->req_idx; in mv_qc_prep()
2081 pp->crqb[in_index].sg_addr = in mv_qc_prep()
2082 cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep()
2083 pp->crqb[in_index].sg_addr_hi = in mv_qc_prep()
2084 cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep()
2085 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); in mv_qc_prep()
2087 cw = &pp->crqb[in_index].ata_cmd[0]; in mv_qc_prep()
2089 /* Sadly, the CRQB cannot accommodate all registers--there are in mv_qc_prep()
2096 switch (tf->command) { in mv_qc_prep()
2102 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2106 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2107 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2110 /* The only other commands EDMA supports in non-queued and in mv_qc_prep()
2111 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none in mv_qc_prep()
2116 tf->command); in mv_qc_prep()
2119 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2120 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2121 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2122 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2123 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2124 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2125 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2126 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); in mv_qc_prep()
2127 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ in mv_qc_prep()
2129 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep()
2137 * mv_qc_prep_iie - Host specific command preparation.
2150 struct ata_port *ap = qc->ap; in mv_qc_prep_iie()
2151 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep_iie()
2153 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep_iie()
2157 if ((tf->protocol != ATA_PROT_DMA) && in mv_qc_prep_iie()
2158 (tf->protocol != ATA_PROT_NCQ)) in mv_qc_prep_iie()
2160 if (tf->command == ATA_CMD_DSM) in mv_qc_prep_iie()
2164 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep_iie()
2167 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep_iie()
2168 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep_iie()
2169 flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT; in mv_qc_prep_iie()
2170 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep_iie()
2173 in_index = pp->req_idx; in mv_qc_prep_iie()
2175 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; in mv_qc_prep_iie()
2176 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep_iie()
2177 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep_iie()
2178 crqb->flags = cpu_to_le32(flags); in mv_qc_prep_iie()
2180 crqb->ata_cmd[0] = cpu_to_le32( in mv_qc_prep_iie()
2181 (tf->command << 16) | in mv_qc_prep_iie()
2182 (tf->feature << 24) in mv_qc_prep_iie()
2184 crqb->ata_cmd[1] = cpu_to_le32( in mv_qc_prep_iie()
2185 (tf->lbal << 0) | in mv_qc_prep_iie()
2186 (tf->lbam << 8) | in mv_qc_prep_iie()
2187 (tf->lbah << 16) | in mv_qc_prep_iie()
2188 (tf->device << 24) in mv_qc_prep_iie()
2190 crqb->ata_cmd[2] = cpu_to_le32( in mv_qc_prep_iie()
2191 (tf->hob_lbal << 0) | in mv_qc_prep_iie()
2192 (tf->hob_lbam << 8) | in mv_qc_prep_iie()
2193 (tf->hob_lbah << 16) | in mv_qc_prep_iie()
2194 (tf->hob_feature << 24) in mv_qc_prep_iie()
2196 crqb->ata_cmd[3] = cpu_to_le32( in mv_qc_prep_iie()
2197 (tf->nsect << 0) | in mv_qc_prep_iie()
2198 (tf->hob_nsect << 8) in mv_qc_prep_iie()
2201 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep_iie()
2209 * mv_sff_check_status - fetch device status, if valid
2210 * @ap: ATA port to fetch status from
2223 u8 stat = ioread8(ap->ioaddr.status_addr); in mv_sff_check_status()
2224 struct mv_port_priv *pp = ap->private_data; in mv_sff_check_status()
2226 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { in mv_sff_check_status()
2228 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; in mv_sff_check_status()
2236 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2238 * @nwords: number of 32-bit words in the fis
2244 int i, timeout = 200, final_word = nwords - 1; in mv_send_fis()
2255 /* Flag end-of-transmission, and then send the final word */ in mv_send_fis()
2265 } while (!(ifstat & 0x1000) && --timeout); in mv_send_fis()
2267 /* Restore original port configuration */ in mv_send_fis()
2280 * mv_qc_issue_fis - Issue a command directly as a FIS
2290 * of non-data commands. So avoid sending them via this function,
2298 struct ata_port *ap = qc->ap; in mv_qc_issue_fis()
2299 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue_fis()
2300 struct ata_link *link = qc->dev->link; in mv_qc_issue_fis()
2304 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); in mv_qc_issue_fis()
2309 switch (qc->tf.protocol) { in mv_qc_issue_fis()
2311 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2314 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2317 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2318 if (qc->tf.flags & ATA_TFLAG_WRITE) in mv_qc_issue_fis()
2319 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2321 ap->hsm_task_state = HSM_ST; in mv_qc_issue_fis()
2324 ap->hsm_task_state = HSM_ST_LAST; in mv_qc_issue_fis()
2328 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue_fis()
2334 * mv_qc_issue - Initiate a command to the host
2348 struct ata_port *ap = qc->ap; in mv_qc_issue()
2350 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue()
2354 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ in mv_qc_issue()
2356 switch (qc->tf.protocol) { in mv_qc_issue()
2358 if (qc->tf.command == ATA_CMD_DSM) { in mv_qc_issue()
2359 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ in mv_qc_issue()
2365 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); in mv_qc_issue()
2366 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_qc_issue()
2367 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_qc_issue()
2370 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, in mv_qc_issue()
2386 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { in mv_qc_issue()
2387 --limit_warnings; in mv_qc_issue()
2388 ata_link_warn(qc->dev->link, DRV_NAME in mv_qc_issue()
2396 if (ap->flags & ATA_FLAG_PIO_POLLING) in mv_qc_issue()
2397 qc->tf.flags |= ATA_TFLAG_POLLING; in mv_qc_issue()
2401 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue()
2407 * We're about to send a non-EDMA capable command to the in mv_qc_issue()
2408 * port. Turn off EDMA so there won't be problems accessing in mv_qc_issue()
2413 mv_pmp_select(ap, qc->dev->link->pmp); in mv_qc_issue()
2415 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { in mv_qc_issue()
2416 struct mv_host_priv *hpriv = ap->host->private_data; in mv_qc_issue()
2421 * from libata-eh *must* use mv_qc_issue_fis(). in mv_qc_issue()
2424 * Rather than special-case it, we'll just *always* in mv_qc_issue()
2436 struct mv_port_priv *pp = ap->private_data; in mv_get_active_qc()
2439 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_get_active_qc()
2441 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_get_active_qc()
2442 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) in mv_get_active_qc()
2450 struct mv_port_priv *pp = ap->private_data; in mv_pmp_error_handler()
2452 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { in mv_pmp_error_handler()
2455 * before we freeze the port entirely. in mv_pmp_error_handler()
2459 pmp_map = pp->delayed_eh_pmp_map; in mv_pmp_error_handler()
2460 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; in mv_pmp_error_handler()
2464 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_error_handler()
2491 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_eh_prep()
2492 struct ata_eh_info *ehi = &link->eh_info; in mv_pmp_eh_prep()
2497 ehi->err_mask |= AC_ERR_DEV; in mv_pmp_eh_prep()
2498 ehi->action |= ATA_EH_RESET; in mv_pmp_eh_prep()
2518 struct mv_port_priv *pp = ap->private_data; in mv_handle_fbs_ncq_dev_err()
2525 * Set a port flag to prevent further I/O being enqueued. in mv_handle_fbs_ncq_dev_err()
2526 * Leave the EDMA running to drain outstanding commands from this port. in mv_handle_fbs_ncq_dev_err()
2527 * Perform the post-mortem/EH only when all responses are complete. in mv_handle_fbs_ncq_dev_err()
2530 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { in mv_handle_fbs_ncq_dev_err()
2531 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; in mv_handle_fbs_ncq_dev_err()
2532 pp->delayed_eh_pmp_map = 0; in mv_handle_fbs_ncq_dev_err()
2534 old_map = pp->delayed_eh_pmp_map; in mv_handle_fbs_ncq_dev_err()
2538 pp->delayed_eh_pmp_map = new_map; in mv_handle_fbs_ncq_dev_err()
2545 __func__, pp->delayed_eh_pmp_map, in mv_handle_fbs_ncq_dev_err()
2546 ap->qc_active, failed_links, in mv_handle_fbs_ncq_dev_err()
2547 ap->nr_active_links); in mv_handle_fbs_ncq_dev_err()
2549 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { in mv_handle_fbs_ncq_dev_err()
2565 * FBS+non-NCQ operation is not yet implemented. in mv_handle_fbs_non_ncq_dev_err()
2568 * Device error during FBS+non-NCQ operation: in mv_handle_fbs_non_ncq_dev_err()
2578 struct mv_port_priv *pp = ap->private_data; in mv_handle_dev_err()
2580 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_handle_dev_err()
2582 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) in mv_handle_dev_err()
2591 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { in mv_handle_dev_err()
2593 * EDMA should NOT have self-disabled for this case. in mv_handle_dev_err()
2599 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2605 * EDMA should have self-disabled for this case. in mv_handle_dev_err()
2611 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2621 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_unexpected_intr()
2628 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_unexpected_intr()
2629 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) in mv_unexpected_intr()
2633 ehi->err_mask |= AC_ERR_OTHER; in mv_unexpected_intr()
2634 ehi->action |= ATA_EH_RESET; in mv_unexpected_intr()
2639 * mv_err_intr - Handle error interrupts on the port
2644 * Also, if the port disabled DMA, update our cached copy to match.
2654 struct mv_port_priv *pp = ap->private_data; in mv_err_intr()
2655 struct mv_host_priv *hpriv = ap->host->private_data; in mv_err_intr()
2657 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_err_intr()
2666 sata_scr_read(&ap->link, SCR_ERROR, &serr); in mv_err_intr()
2667 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); in mv_err_intr()
2678 * Device errors during FIS-based switching operation in mv_err_intr()
2688 edma_err_cause, pp->pp_flags); in mv_err_intr()
2724 * Gen-I has a different SELF_DIS bit, in mv_err_intr()
2730 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2731 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2736 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2737 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2751 ehi->serror |= serr; in mv_err_intr()
2752 ehi->action |= action; in mv_err_intr()
2755 qc->err_mask |= err_mask; in mv_err_intr()
2757 ehi->err_mask |= err_mask; in mv_err_intr()
2778 ata_link_abort(qc->dev->link); in mv_err_intr()
2788 u16 edma_status = le16_to_cpu(response->flags); in mv_process_crpb_response()
2792 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). in mv_process_crpb_response()
2815 struct mv_host_priv *hpriv = ap->host->private_data; in mv_process_crpb_entries()
2819 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); in mv_process_crpb_entries()
2826 while (in_index != pp->resp_idx) { in mv_process_crpb_entries()
2828 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; in mv_process_crpb_entries()
2830 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_process_crpb_entries()
2834 tag = ap->link.active_tag; in mv_process_crpb_entries()
2837 tag = le16_to_cpu(response->id) & 0x1f; in mv_process_crpb_entries()
2848 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | in mv_process_crpb_entries()
2849 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), in mv_process_crpb_entries()
2861 * so that we have a consistent view for this port, in mv_port_intr()
2864 pp = ap->private_data; in mv_port_intr()
2865 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); in mv_port_intr()
2871 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_port_intr()
2875 * Handle chip-reported errors, or continue on to handle PIO. in mv_port_intr()
2889 * mv_host_intr - Handle all interrupts on the given host controller
2890 * @host: host specific structure
2896 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) in mv_host_intr() argument
2898 struct mv_host_priv *hpriv = host->private_data; in mv_host_intr()
2899 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_host_intr()
2900 unsigned int handled = 0, port; in mv_host_intr() local
2906 for (port = 0; port < hpriv->n_ports; port++) { in mv_host_intr()
2907 struct ata_port *ap = host->ports[port]; in mv_host_intr()
2910 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); in mv_host_intr()
2912 * Each hc within the host has its own hc_irq_cause register, in mv_host_intr()
2915 if (hardport == 0) { /* first port on this hc ? */ in mv_host_intr()
2922 port += MV_PORTS_PER_HC - 1; in mv_host_intr()
2941 if ((port + p) >= hpriv->n_ports) in mv_host_intr()
2947 hc_mmio = mv_hc_base_from_port(mmio, port); in mv_host_intr()
2952 * Handle interrupts signalled for this port: in mv_host_intr()
2961 static int mv_pci_error(struct ata_host *host, void __iomem *mmio) in mv_pci_error() argument
2963 struct mv_host_priv *hpriv = host->private_data; in mv_pci_error()
2970 err_cause = readl(mmio + hpriv->irq_cause_offset); in mv_pci_error()
2972 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); in mv_pci_error()
2975 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); in mv_pci_error()
2977 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_pci_error()
2979 for (i = 0; i < host->n_ports; i++) { in mv_pci_error()
2980 ap = host->ports[i]; in mv_pci_error()
2981 if (!ata_link_offline(&ap->link)) { in mv_pci_error()
2982 ehi = &ap->link.eh_info; in mv_pci_error()
2988 ehi->action = ATA_EH_RESET; in mv_pci_error()
2989 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_pci_error()
2991 qc->err_mask |= err_mask; in mv_pci_error()
2993 ehi->err_mask |= err_mask; in mv_pci_error()
3002 * mv_interrupt - Main interrupt event handler
3004 * @dev_instance: private data; in this case the host structure
3006 * Read the read only register to determine if any host
3012 * This routine holds the host lock while processing pending
3017 struct ata_host *host = dev_instance; in mv_interrupt() local
3018 struct mv_host_priv *hpriv = host->private_data; in mv_interrupt()
3020 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; in mv_interrupt()
3023 spin_lock(&host->lock); in mv_interrupt()
3029 main_irq_cause = readl(hpriv->main_irq_cause_addr); in mv_interrupt()
3030 pending_irqs = main_irq_cause & hpriv->main_irq_mask; in mv_interrupt()
3037 handled = mv_pci_error(host, hpriv->base); in mv_interrupt()
3039 handled = mv_host_intr(host, pending_irqs); in mv_interrupt()
3044 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); in mv_interrupt()
3046 spin_unlock(&host->lock); in mv_interrupt()
3070 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_read()
3071 void __iomem *mmio = hpriv->base; in mv5_scr_read()
3072 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_read()
3079 return -EINVAL; in mv5_scr_read()
3084 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_write()
3085 void __iomem *mmio = hpriv->base; in mv5_scr_write()
3086 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_write()
3093 return -EINVAL; in mv5_scr_write()
3096 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) in mv5_reset_bus() argument
3098 struct pci_dev *pdev = to_pci_dev(host->dev); in mv5_reset_bus()
3101 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); in mv5_reset_bus()
3109 mv_reset_pci_bus(host, mmio); in mv5_reset_bus()
3125 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ in mv5_read_preamp()
3126 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ in mv5_read_preamp()
3143 unsigned int port) in mv5_phy_errata() argument
3145 void __iomem *phy_mmio = mv5_phy_base(mmio, port); in mv5_phy_errata()
3148 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); in mv5_phy_errata()
3163 tmp |= hpriv->signal[port].pre; in mv5_phy_errata()
3164 tmp |= hpriv->signal[port].amps; in mv5_phy_errata()
3172 unsigned int port) in mv5_reset_hc_port() argument
3174 void __iomem *port_mmio = mv_port_base(mmio, port); in mv5_reset_hc_port()
3176 mv_reset_channel(hpriv, mmio, port); in mv5_reset_hc_port()
3216 unsigned int hc, port; in mv5_reset_hc() local
3219 for (port = 0; port < MV_PORTS_PER_HC; port++) in mv5_reset_hc()
3221 (hc * MV_PORTS_PER_HC) + port); in mv5_reset_hc()
3231 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) in mv_reset_pci_bus() argument
3233 struct mv_host_priv *hpriv = host->private_data; in mv_reset_pci_bus()
3244 ZERO(hpriv->irq_cause_offset); in mv_reset_pci_bus()
3245 ZERO(hpriv->irq_mask_offset); in mv_reset_pci_bus()
3266 * mv6_reset_hc - Perform the 6xxx global soft reset
3305 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3319 } while ((GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3337 hpriv->signal[idx].amps = 0x7 << 8; in mv6_read_preamp()
3338 hpriv->signal[idx].pre = 0x1 << 5; in mv6_read_preamp()
3345 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv6_read_preamp()
3346 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv6_read_preamp()
3355 unsigned int port) in mv6_phy_errata() argument
3357 void __iomem *port_mmio = mv_port_base(mmio, port); in mv6_phy_errata()
3359 u32 hp_flags = hpriv->hp_flags; in mv6_phy_errata()
3382 * Gen-II/IIe PHY_MODE3 errata RM#2: in mv6_phy_errata()
3388 /* Guideline 88F5182 (GL# SATA-S11) */ in mv6_phy_errata()
3395 * Enforce reserved-bit restrictions on GenIIe devices only. in mv6_phy_errata()
3406 * Workaround for 60x1-B2 errata SATA#13: in mv6_phy_errata()
3413 /* Revert values of pre-emphasis and signal amps to the saved ones */ in mv6_phy_errata()
3417 m2 |= hpriv->signal[port].amps; in mv6_phy_errata()
3418 m2 |= hpriv->signal[port].pre; in mv6_phy_errata()
3447 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv_soc_read_preamp()
3448 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv_soc_read_preamp()
3454 void __iomem *mmio, unsigned int port) in mv_soc_reset_hc_port() argument
3456 void __iomem *port_mmio = mv_port_base(mmio, port); in mv_soc_reset_hc_port()
3458 mv_reset_channel(hpriv, mmio, port); in mv_soc_reset_hc_port()
3494 unsigned int port; in mv_soc_reset_hc() local
3496 for (port = 0; port < hpriv->n_ports; port++) in mv_soc_reset_hc()
3497 mv_soc_reset_hc_port(hpriv, mmio, port); in mv_soc_reset_hc()
3510 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) in mv_soc_reset_bus() argument
3516 void __iomem *mmio, unsigned int port) in mv_soc_65n_phy_errata() argument
3518 void __iomem *port_mmio = mv_port_base(mmio, port); in mv_soc_65n_phy_errata()
3547 * soc_is_65 - check if the soc is 65 nano device
3550 * register, this register should contain non-zero value and it exists only
3555 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); in soc_is_65n()
3598 hpriv->ops->phy_errata(hpriv, mmio, port_no); in mv_reset_channel()
3621 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_pmp_hardreset()
3628 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_softreset()
3635 struct ata_port *ap = link->ap; in mv_hardreset()
3636 struct mv_host_priv *hpriv = ap->host->private_data; in mv_hardreset()
3637 struct mv_port_priv *pp = ap->private_data; in mv_hardreset()
3638 void __iomem *mmio = hpriv->base; in mv_hardreset()
3643 mv_reset_channel(hpriv, mmio, ap->port_no); in mv_hardreset()
3644 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_hardreset()
3645 pp->pp_flags &= in mv_hardreset()
3651 sata_ehc_deb_timing(&link->eh_context); in mv_hardreset()
3655 rc = online ? -EAGAIN : rc; in mv_hardreset()
3680 struct mv_host_priv *hpriv = ap->host->private_data; in mv_eh_thaw()
3681 unsigned int port = ap->port_no; in mv_eh_thaw() local
3682 unsigned int hardport = mv_hardport_from_port(port); in mv_eh_thaw()
3683 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); in mv_eh_thaw()
3687 /* clear EDMA errors on this port */ in mv_eh_thaw()
3698 * mv_port_init - Perform some early initialization on a single port.
3699 * @port: libata data structure storing shadow register addresses
3700 * @port_mmio: base address of the port
3703 * interrupts on the port, and unmask interrupts for the future
3704 * start of the port.
3709 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) in mv_port_init() argument
3715 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); in mv_port_init()
3716 port->error_addr = in mv_port_init()
3717 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); in mv_port_init()
3718 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); in mv_port_init()
3719 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); in mv_port_init()
3720 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); in mv_port_init()
3721 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); in mv_port_init()
3722 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); in mv_port_init()
3723 port->status_addr = in mv_port_init()
3724 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); in mv_port_init()
3726 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; in mv_port_init()
3728 /* Clear any currently outstanding port interrupt conditions */ in mv_port_init()
3733 /* unmask all non-transient EDMA error interrupts */ in mv_port_init()
3742 static unsigned int mv_in_pcix_mode(struct ata_host *host) in mv_in_pcix_mode() argument
3744 struct mv_host_priv *hpriv = host->private_data; in mv_in_pcix_mode()
3745 void __iomem *mmio = hpriv->base; in mv_in_pcix_mode()
3749 return 0; /* not PCI-X capable */ in mv_in_pcix_mode()
3753 return 1; /* chip is in PCI-X mode */ in mv_in_pcix_mode()
3756 static int mv_pci_cut_through_okay(struct ata_host *host) in mv_pci_cut_through_okay() argument
3758 struct mv_host_priv *hpriv = host->private_data; in mv_pci_cut_through_okay()
3759 void __iomem *mmio = hpriv->base; in mv_pci_cut_through_okay()
3762 if (!mv_in_pcix_mode(host)) { in mv_pci_cut_through_okay()
3770 static void mv_60x1b2_errata_pci7(struct ata_host *host) in mv_60x1b2_errata_pci7() argument
3772 struct mv_host_priv *hpriv = host->private_data; in mv_60x1b2_errata_pci7()
3773 void __iomem *mmio = hpriv->base; in mv_60x1b2_errata_pci7()
3775 /* workaround for 60x1-B2 errata PCI#7 */ in mv_60x1b2_errata_pci7()
3776 if (mv_in_pcix_mode(host)) { in mv_60x1b2_errata_pci7()
3782 static int mv_chip_id(struct ata_host *host, unsigned int board_idx) in mv_chip_id() argument
3784 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_chip_id()
3785 struct mv_host_priv *hpriv = host->private_data; in mv_chip_id()
3786 u32 hp_flags = hpriv->hp_flags; in mv_chip_id()
3790 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3793 switch (pdev->revision) { in mv_chip_id()
3801 dev_warn(&pdev->dev, in mv_chip_id()
3810 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3813 switch (pdev->revision) { in mv_chip_id()
3821 dev_warn(&pdev->dev, in mv_chip_id()
3830 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3833 switch (pdev->revision) { in mv_chip_id()
3835 mv_60x1b2_errata_pci7(host); in mv_chip_id()
3842 dev_warn(&pdev->dev, in mv_chip_id()
3851 if (pdev->vendor == PCI_VENDOR_ID_TTI && in mv_chip_id()
3852 (pdev->device == 0x2300 || pdev->device == 0x2310)) in mv_chip_id()
3867 * RAID metadata is at: (dev->n_sectors & ~0xfffff) in mv_chip_id()
3876 " use sectors 8-9 on \"Legacy\" drives," in mv_chip_id()
3882 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3884 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) in mv_chip_id()
3887 switch (pdev->revision) { in mv_chip_id()
3892 dev_warn(&pdev->dev, in mv_chip_id()
3900 hpriv->ops = &mv_soc_65n_ops; in mv_chip_id()
3902 hpriv->ops = &mv_soc_ops; in mv_chip_id()
3908 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx); in mv_chip_id()
3912 hpriv->hp_flags = hp_flags; in mv_chip_id()
3914 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; in mv_chip_id()
3915 hpriv->irq_mask_offset = PCIE_IRQ_MASK; in mv_chip_id()
3916 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; in mv_chip_id()
3918 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; in mv_chip_id()
3919 hpriv->irq_mask_offset = PCI_IRQ_MASK; in mv_chip_id()
3920 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; in mv_chip_id()
3927 * mv_init_host - Perform some early initialization of the host.
3928 * @host: ATA host to initialize
3930 * If possible, do an early global reset of the host. Then do
3931 * our port init and clear/unmask all/relevant host interrupts.
3936 static int mv_init_host(struct ata_host *host) in mv_init_host() argument
3938 int rc = 0, n_hc, port, hc; in mv_init_host() local
3939 struct mv_host_priv *hpriv = host->private_data; in mv_init_host()
3940 void __iomem *mmio = hpriv->base; in mv_init_host()
3942 rc = mv_chip_id(host, hpriv->board_idx); in mv_init_host()
3947 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3948 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; in mv_init_host()
3950 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3951 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; in mv_init_host()
3955 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); in mv_init_host()
3958 mv_set_main_irq_mask(host, ~0, 0); in mv_init_host()
3960 n_hc = mv_get_hc_count(host->ports[0]->flags); in mv_init_host()
3962 for (port = 0; port < host->n_ports; port++) in mv_init_host()
3963 if (hpriv->ops->read_preamp) in mv_init_host()
3964 hpriv->ops->read_preamp(hpriv, port, mmio); in mv_init_host()
3966 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); in mv_init_host()
3970 hpriv->ops->reset_flash(hpriv, mmio); in mv_init_host()
3971 hpriv->ops->reset_bus(host, mmio); in mv_init_host()
3972 hpriv->ops->enable_leds(hpriv, mmio); in mv_init_host()
3974 for (port = 0; port < host->n_ports; port++) { in mv_init_host()
3975 struct ata_port *ap = host->ports[port]; in mv_init_host()
3976 void __iomem *port_mmio = mv_port_base(mmio, port); in mv_init_host()
3978 mv_port_init(&ap->ioaddr, port_mmio); in mv_init_host()
3994 /* Clear any currently outstanding host interrupt conditions */ in mv_init_host()
3995 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_init_host()
3997 /* and unmask interrupt generation for host regs */ in mv_init_host()
3998 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); in mv_init_host()
4002 * enable only global host interrupts for now. in mv_init_host()
4003 * The per-port interrupts get done later as ports are set up. in mv_init_host()
4005 mv_set_main_irq_mask(host, 0, PCI_ERR); in mv_init_host()
4006 mv_set_irq_coalescing(host, irq_coalescing_io_count, in mv_init_host()
4014 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, in mv_create_dma_pools()
4016 if (!hpriv->crqb_pool) in mv_create_dma_pools()
4017 return -ENOMEM; in mv_create_dma_pools()
4019 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, in mv_create_dma_pools()
4021 if (!hpriv->crpb_pool) in mv_create_dma_pools()
4022 return -ENOMEM; in mv_create_dma_pools()
4024 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, in mv_create_dma_pools()
4026 if (!hpriv->sg_tbl_pool) in mv_create_dma_pools()
4027 return -ENOMEM; in mv_create_dma_pools()
4038 writel(0, hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4039 writel(0, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4042 for (i = 0; i < dram->num_cs; i++) { in mv_conf_mbus_windows()
4043 const struct mbus_dram_window *cs = dram->cs + i; in mv_conf_mbus_windows()
4045 writel(((cs->size - 1) & 0xffff0000) | in mv_conf_mbus_windows()
4046 (cs->mbus_attr << 8) | in mv_conf_mbus_windows()
4047 (dram->mbus_dram_target_id << 4) | 1, in mv_conf_mbus_windows()
4048 hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4049 writel(cs->base, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4054 * mv_platform_probe - handle a positive probe of an soc Marvell
4055 * host
4067 struct ata_host *host; in mv_platform_probe() local
4072 int port; in mv_platform_probe() local
4074 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_platform_probe()
4079 if (unlikely(pdev->num_resources != 2)) { in mv_platform_probe()
4080 dev_err(&pdev->dev, "invalid number of resources\n"); in mv_platform_probe()
4081 return -EINVAL; in mv_platform_probe()
4089 return -EINVAL; in mv_platform_probe()
4091 /* allocate host */ in mv_platform_probe()
4092 if (pdev->dev.of_node) { in mv_platform_probe()
4093 rc = of_property_read_u32(pdev->dev.of_node, "nr-ports", in mv_platform_probe()
4096 dev_err(&pdev->dev, in mv_platform_probe()
4097 "error parsing nr-ports property: %d\n", rc); in mv_platform_probe()
4102 dev_err(&pdev->dev, "nr-ports must be positive: %d\n", in mv_platform_probe()
4104 return -EINVAL; in mv_platform_probe()
4107 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); in mv_platform_probe()
4109 mv_platform_data = dev_get_platdata(&pdev->dev); in mv_platform_probe()
4110 n_ports = mv_platform_data->n_ports; in mv_platform_probe()
4114 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_platform_probe()
4115 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_platform_probe()
4117 if (!host || !hpriv) in mv_platform_probe()
4118 return -ENOMEM; in mv_platform_probe()
4119 hpriv->port_clks = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4122 if (!hpriv->port_clks) in mv_platform_probe()
4123 return -ENOMEM; in mv_platform_probe()
4124 hpriv->port_phys = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4127 if (!hpriv->port_phys) in mv_platform_probe()
4128 return -ENOMEM; in mv_platform_probe()
4129 host->private_data = hpriv; in mv_platform_probe()
4130 hpriv->board_idx = chip_soc; in mv_platform_probe()
4132 host->iomap = NULL; in mv_platform_probe()
4133 hpriv->base = devm_ioremap(&pdev->dev, res->start, in mv_platform_probe()
4135 if (!hpriv->base) in mv_platform_probe()
4136 return -ENOMEM; in mv_platform_probe()
4138 hpriv->base -= SATAHC0_REG_BASE; in mv_platform_probe()
4140 hpriv->clk = clk_get(&pdev->dev, NULL); in mv_platform_probe()
4141 if (IS_ERR(hpriv->clk)) in mv_platform_probe()
4142 dev_notice(&pdev->dev, "cannot get optional clkdev\n"); in mv_platform_probe()
4144 clk_prepare_enable(hpriv->clk); in mv_platform_probe()
4146 for (port = 0; port < n_ports; port++) { in mv_platform_probe()
4148 sprintf(port_number, "%d", port); in mv_platform_probe()
4149 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); in mv_platform_probe()
4150 if (!IS_ERR(hpriv->port_clks[port])) in mv_platform_probe()
4151 clk_prepare_enable(hpriv->port_clks[port]); in mv_platform_probe()
4153 sprintf(port_number, "port%d", port); in mv_platform_probe()
4154 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, in mv_platform_probe()
4156 if (IS_ERR(hpriv->port_phys[port])) { in mv_platform_probe()
4157 rc = PTR_ERR(hpriv->port_phys[port]); in mv_platform_probe()
4158 hpriv->port_phys[port] = NULL; in mv_platform_probe()
4159 if (rc != -EPROBE_DEFER) in mv_platform_probe()
4160 dev_warn(&pdev->dev, "error getting phy %d", rc); in mv_platform_probe()
4163 hpriv->n_ports = port; in mv_platform_probe()
4166 phy_power_on(hpriv->port_phys[port]); in mv_platform_probe()
4170 hpriv->n_ports = n_ports; in mv_platform_probe()
4173 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_probe()
4179 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_platform_probe()
4187 if (pdev->dev.of_node && in mv_platform_probe()
4188 of_device_is_compatible(pdev->dev.of_node, in mv_platform_probe()
4189 "marvell,armada-370-sata")) in mv_platform_probe()
4190 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; in mv_platform_probe()
4193 rc = mv_init_host(host); in mv_platform_probe()
4197 dev_info(&pdev->dev, "slots %u ports %d\n", in mv_platform_probe()
4198 (unsigned)MV_MAX_Q_DEPTH, host->n_ports); in mv_platform_probe()
4200 rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht); in mv_platform_probe()
4205 if (!IS_ERR(hpriv->clk)) { in mv_platform_probe()
4206 clk_disable_unprepare(hpriv->clk); in mv_platform_probe()
4207 clk_put(hpriv->clk); in mv_platform_probe()
4209 for (port = 0; port < hpriv->n_ports; port++) { in mv_platform_probe()
4210 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_probe()
4211 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_probe()
4212 clk_put(hpriv->port_clks[port]); in mv_platform_probe()
4214 phy_power_off(hpriv->port_phys[port]); in mv_platform_probe()
4222 * mv_platform_remove - unplug a platform interface
4230 struct ata_host *host = platform_get_drvdata(pdev); in mv_platform_remove() local
4231 struct mv_host_priv *hpriv = host->private_data; in mv_platform_remove()
4232 int port; in mv_platform_remove() local
4233 ata_host_detach(host); in mv_platform_remove()
4235 if (!IS_ERR(hpriv->clk)) { in mv_platform_remove()
4236 clk_disable_unprepare(hpriv->clk); in mv_platform_remove()
4237 clk_put(hpriv->clk); in mv_platform_remove()
4239 for (port = 0; port < host->n_ports; port++) { in mv_platform_remove()
4240 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_remove()
4241 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_remove()
4242 clk_put(hpriv->port_clks[port]); in mv_platform_remove()
4244 phy_power_off(hpriv->port_phys[port]); in mv_platform_remove()
4252 struct ata_host *host = platform_get_drvdata(pdev); in mv_platform_suspend() local
4253 if (host) in mv_platform_suspend()
4254 return ata_host_suspend(host, state); in mv_platform_suspend()
4261 struct ata_host *host = platform_get_drvdata(pdev); in mv_platform_resume() local
4265 if (host) { in mv_platform_resume()
4266 struct mv_host_priv *hpriv = host->private_data; in mv_platform_resume()
4269 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_resume()
4276 ret = mv_init_host(host); in mv_platform_resume()
4281 ata_host_resume(host); in mv_platform_resume()
4293 { .compatible = "marvell,armada-370-sata", },
4294 { .compatible = "marvell,orion-sata", },
4337 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { in pci_go_64()
4338 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); in pci_go_64()
4340 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); in pci_go_64()
4342 dev_err(&pdev->dev, in pci_go_64()
4343 "64-bit DMA enable failed\n"); in pci_go_64()
4348 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in pci_go_64()
4350 dev_err(&pdev->dev, "32-bit DMA enable failed\n"); in pci_go_64()
4353 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); in pci_go_64()
4355 dev_err(&pdev->dev, in pci_go_64()
4356 "32-bit consistent DMA enable failed\n"); in pci_go_64()
4365 * mv_print_info - Dump key info to kernel log for perusal.
4366 * @host: ATA host to print info about
4373 static void mv_print_info(struct ata_host *host) in mv_print_info() argument
4375 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_print_info()
4376 struct mv_host_priv *hpriv = host->private_data; in mv_print_info()
4400 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n", in mv_print_info()
4401 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, in mv_print_info()
4402 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); in mv_print_info()
4406 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4408 * @ent: PCI device ID entry for the matched host
4416 unsigned int board_idx = (unsigned int)ent->driver_data; in mv_pci_init_one()
4418 struct ata_host *host; in mv_pci_init_one() local
4420 int n_ports, port, rc; in mv_pci_init_one() local
4422 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_pci_init_one()
4424 /* allocate host */ in mv_pci_init_one()
4425 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; in mv_pci_init_one()
4427 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_pci_init_one()
4428 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_pci_init_one()
4429 if (!host || !hpriv) in mv_pci_init_one()
4430 return -ENOMEM; in mv_pci_init_one()
4431 host->private_data = hpriv; in mv_pci_init_one()
4432 hpriv->n_ports = n_ports; in mv_pci_init_one()
4433 hpriv->board_idx = board_idx; in mv_pci_init_one()
4441 if (rc == -EBUSY) in mv_pci_init_one()
4445 host->iomap = pcim_iomap_table(pdev); in mv_pci_init_one()
4446 hpriv->base = host->iomap[MV_PRIMARY_BAR]; in mv_pci_init_one()
4452 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_pci_init_one()
4456 for (port = 0; port < host->n_ports; port++) { in mv_pci_init_one()
4457 struct ata_port *ap = host->ports[port]; in mv_pci_init_one()
4458 void __iomem *port_mmio = mv_port_base(hpriv->base, port); in mv_pci_init_one()
4459 unsigned int offset = port_mmio - hpriv->base; in mv_pci_init_one()
4461 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); in mv_pci_init_one()
4462 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); in mv_pci_init_one()
4466 rc = mv_init_host(host); in mv_pci_init_one()
4470 /* Enable message-switched interrupts, if requested */ in mv_pci_init_one()
4472 hpriv->hp_flags |= MV_HP_FLAG_MSI; in mv_pci_init_one()
4475 mv_print_info(host); in mv_pci_init_one()
4479 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, in mv_pci_init_one()
4486 struct ata_host *host = pci_get_drvdata(pdev); in mv_pci_device_resume() local
4494 rc = mv_init_host(host); in mv_pci_device_resume()
4498 ata_host_resume(host); in mv_pci_device_resume()
4507 int rc = -ENODEV; in mv_init()
4531 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");