13 #include <linux/clk-provider.h>
52 	unsigned long accuracy;  member
69 	void __iomem *sckcr = osc->sckcr;  in clk_slow_osc_prepare()
78 		udelay(osc->startup_usec);  in clk_slow_osc_prepare()
80 		usleep_range(osc->startup_usec, osc->startup_usec + 1);  in clk_slow_osc_prepare()
88 	void __iomem *sckcr = osc->sckcr;  in clk_slow_osc_unprepare()
100 	void __iomem *sckcr = osc->sckcr;  in clk_slow_osc_is_prepared()
128 		return ERR_PTR(-EINVAL);  in at91_clk_register_slow_osc()
132 		return ERR_PTR(-ENOMEM);  in at91_clk_register_slow_osc()
140 	osc->hw.init = &init;  in at91_clk_register_slow_osc()
141 	osc->sckcr = sckcr;  in at91_clk_register_slow_osc()
142 	osc->startup_usec = startup;  in at91_clk_register_slow_osc()
148 	hw = &osc->hw;  in at91_clk_register_slow_osc()
149 	ret = clk_hw_register(NULL, &osc->hw);  in at91_clk_register_slow_osc()
163 	const char *name = np->name;  in of_at91sam9x5_clk_slow_osc_setup()
168 	of_property_read_string(np, "clock-output-names", &name);  in of_at91sam9x5_clk_slow_osc_setup()
169 	of_property_read_u32(np, "atmel,startup-time-usec", &startup);  in of_at91sam9x5_clk_slow_osc_setup()
170 	bypass = of_property_read_bool(np, "atmel,osc-bypass");  in of_at91sam9x5_clk_slow_osc_setup()
185 	return osc->frequency;  in clk_slow_rc_osc_recalc_rate()
193 	return osc->accuracy;  in clk_slow_rc_osc_recalc_accuracy()
199 	void __iomem *sckcr = osc->sckcr;  in clk_slow_rc_osc_prepare()
204 		udelay(osc->startup_usec);  in clk_slow_rc_osc_prepare()
206 		usleep_range(osc->startup_usec, osc->startup_usec + 1);  in clk_slow_rc_osc_prepare()
214 	void __iomem *sckcr = osc->sckcr;  in clk_slow_rc_osc_unprepare()
223 	return !!(readl(osc->sckcr) & AT91_SCKC_RCEN);  in clk_slow_rc_osc_is_prepared()
238 			      unsigned long accuracy,  in at91_clk_register_slow_rc_osc()  argument
247 		return ERR_PTR(-EINVAL);  in at91_clk_register_slow_rc_osc()
251 		return ERR_PTR(-ENOMEM);  in at91_clk_register_slow_rc_osc()
259 	osc->hw.init = &init;  in at91_clk_register_slow_rc_osc()
260 	osc->sckcr = sckcr;  in at91_clk_register_slow_rc_osc()
261 	osc->frequency = frequency;  in at91_clk_register_slow_rc_osc()
262 	osc->accuracy = accuracy;  in at91_clk_register_slow_rc_osc()
263 	osc->startup_usec = startup;  in at91_clk_register_slow_rc_osc()
265 	hw = &osc->hw;  in at91_clk_register_slow_rc_osc()
266 	ret = clk_hw_register(NULL, &osc->hw);  in at91_clk_register_slow_rc_osc()
280 	u32 accuracy = 0;  in of_at91sam9x5_clk_slow_rc_osc_setup()  local
282 	const char *name = np->name;  in of_at91sam9x5_clk_slow_rc_osc_setup()
284 	of_property_read_string(np, "clock-output-names", &name);  in of_at91sam9x5_clk_slow_rc_osc_setup()
285 	of_property_read_u32(np, "clock-frequency", &frequency);  in of_at91sam9x5_clk_slow_rc_osc_setup()
286 	of_property_read_u32(np, "clock-accuracy", &accuracy);  in of_at91sam9x5_clk_slow_rc_osc_setup()
287 	of_property_read_u32(np, "atmel,startup-time-usec", &startup);  in of_at91sam9x5_clk_slow_rc_osc_setup()
289 	hw = at91_clk_register_slow_rc_osc(sckcr, name, frequency, accuracy,  in of_at91sam9x5_clk_slow_rc_osc_setup()
300 	void __iomem *sckcr = slowck->sckcr;  in clk_sam9x5_slow_set_parent()
304 		return -EINVAL;  in clk_sam9x5_slow_set_parent()
331 	return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL);  in clk_sam9x5_slow_get_parent()
351 		return ERR_PTR(-EINVAL);  in at91_clk_register_sam9x5_slow()
355 		return ERR_PTR(-ENOMEM);  in at91_clk_register_sam9x5_slow()
363 	slowck->hw.init = &init;  in at91_clk_register_sam9x5_slow()
364 	slowck->sckcr = sckcr;  in at91_clk_register_sam9x5_slow()
365 	slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL);  in at91_clk_register_sam9x5_slow()
367 	hw = &slowck->hw;  in at91_clk_register_sam9x5_slow()
368 	ret = clk_hw_register(NULL, &slowck->hw);  in at91_clk_register_sam9x5_slow()
383 	const char *name = np->name;  in of_at91sam9x5_clk_slow_setup()
391 	of_property_read_string(np, "clock-output-names", &name);  in of_at91sam9x5_clk_slow_setup()
402 	/* Slow clock */
404 		.compatible = "atmel,at91sam9x5-clk-slow-osc",
408 		.compatible = "atmel,at91sam9x5-clk-slow-rc-osc",
412 		.compatible = "atmel,at91sam9x5-clk-slow",
432 		clk_setup = clk_id->data;  in of_at91sam9x5_sckc_setup()
436 CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
443 	if (osc->prepared)  in clk_sama5d4_slow_osc_prepare()
450 	if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) {  in clk_sama5d4_slow_osc_prepare()
451 		osc->prepared = true;  in clk_sama5d4_slow_osc_prepare()
456 		udelay(osc->startup_usec);  in clk_sama5d4_slow_osc_prepare()
458 		usleep_range(osc->startup_usec, osc->startup_usec + 1);  in clk_sama5d4_slow_osc_prepare()
459 	osc->prepared = true;  in clk_sama5d4_slow_osc_prepare()
468 	return osc->prepared;  in clk_sama5d4_slow_osc_is_prepared()
498 	bypass = of_property_read_bool(np, "atmel,osc-bypass");  in of_sama5d4_sckc_setup()
510 	osc->hw.init = &init;  in of_sama5d4_sckc_setup()
511 	osc->sckcr = regbase;  in of_sama5d4_sckc_setup()
512 	osc->startup_usec = 1200000;  in of_sama5d4_sckc_setup()
517 	hw = &osc->hw;  in of_sama5d4_sckc_setup()
518 	ret = clk_hw_register(NULL, &osc->hw);  in of_sama5d4_sckc_setup()
530 CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",