Lines Matching +full:0 +full:x2000
21 #define PLL_IDIV_REG 0x0
22 #define PLL_FBDIV_REG 0x4
23 #define PLL_ODIV0_REG 0x8
24 #define PLL_ODIV1_REG 0xC
36 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
37 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
38 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
39 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
40 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
41 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
42 { 2116800, 0x82, 0x3CF, 0x10C30, 0x2000 },
43 { 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
44 { 0, 0, 0, 0, 0 },
49 { 1024000, 0x82, 0x105, 0x107DF, 0x2000 },
50 { 1411200, 0x28A, 0x1, 0x10001, 0x2000 },
51 { 1536000, 0xA28, 0x187, 0x10042, 0x2000 },
52 { 2048000, 0x41, 0x105, 0x107DF, 0x2000 },
53 { 2822400, 0x145, 0x1, 0x10001, 0x2000 },
54 { 3072000, 0x514, 0x187, 0x10042, 0x2000 },
55 { 2116800, 0x514, 0x42, 0x10001, 0x2000 },
56 { 2304000, 0x619, 0x82, 0x10001, 0x2000 },
57 { 0, 0, 0, 0, 0 },
85 return (val & 0x3F) + ((val >> 6) & 0x3F); in i2s_pll_get_value()
125 for (i = 0; pll_cfg[i].rate != 0; i++) in i2s_pll_round_rate()
144 for (i = 0; pll_cfg[i].rate != 0; i++) { in i2s_pll_set_rate()
150 return 0; in i2s_pll_set_rate()
180 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); in i2s_pll_clk_probe()
185 memset(&init, 0, sizeof(init)); in i2s_pll_clk_probe()
189 parent_name = of_clk_get_parent_name(node, 0); in i2s_pll_clk_probe()
208 return 0; in i2s_pll_clk_remove()