4  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10  * Adjustable divider clock implementation
13 #include <linux/clk-provider.h>
22  * DOC: basic adjustable divider clock that cannot gate
24  * Traits of this clock:
25  * prepare - clk_prepare only ensures that parents are prepared
26  * enable - clk_enable only ensures that parents are enabled
27  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
28  * parent - fixed parent.  No clk_set_parent support
37 	for (clkt = table; clkt->div; clkt++)  in _get_table_maxdiv()
38 		if (clkt->div > maxdiv && clkt->val <= mask)  in _get_table_maxdiv()
39 			maxdiv = clkt->div;  in _get_table_maxdiv()
48 	for (clkt = table; clkt->div; clkt++)  in _get_table_mindiv()
49 		if (clkt->div < mindiv)  in _get_table_mindiv()
50 			mindiv = clkt->div;  in _get_table_mindiv()
71 	for (clkt = table; clkt->div; clkt++)  in _get_table_div()
72 		if (clkt->val == val)  in _get_table_div()
73 			return clkt->div;  in _get_table_div()
96 	for (clkt = table; clkt->div; clkt++)  in _get_table_val()
97 		if (clkt->div == div)  in _get_table_val()
98 			return clkt->val;  in _get_table_val()
113 	return div - 1;  in _get_val()
141 	val = clk_readl(divider->reg) >> divider->shift;  in clk_divider_recalc_rate()
142 	val &= clk_div_mask(divider->width);  in clk_divider_recalc_rate()
144 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_divider_recalc_rate()
145 				   divider->flags, divider->width);  in clk_divider_recalc_rate()
153 	for (clkt = table; clkt->div; clkt++)  in _is_valid_table_div()
154 		if (clkt->div == div)  in _is_valid_table_div()
174 	for (clkt = table; clkt->div; clkt++) {  in _round_up_table()
175 		if (clkt->div == div)  in _round_up_table()
176 			return clkt->div;  in _round_up_table()
177 		else if (clkt->div < div)  in _round_up_table()
180 		if ((clkt->div - div) < (up - div))  in _round_up_table()
181 			up = clkt->div;  in _round_up_table()
192 	for (clkt = table; clkt->div; clkt++) {  in _round_down_table()
193 		if (clkt->div == div)  in _round_down_table()
194 			return clkt->div;  in _round_down_table()
195 		else if (clkt->div > div)  in _round_down_table()
198 		if ((div - clkt->div) < (div - down))  in _round_down_table()
199 			down = clkt->div;  in _round_down_table()
240 	return (rate - up_rate) <= (down_rate - rate) ? up : down;  in _div_round_closest()
257 		return abs(rate - now) < abs(rate - best);  in _is_best_div()
309 			 * divided from parent clock without needing to change  in clk_divider_bestdiv()
354 	/* Even a read-only clock can propagate a rate change */  in divider_ro_round_rate_parent()
357 			return -EINVAL;  in divider_ro_round_rate_parent()
373 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_divider_round_rate()
376 		val = clk_readl(divider->reg) >> divider->shift;  in clk_divider_round_rate()
377 		val &= clk_div_mask(divider->width);  in clk_divider_round_rate()
379 		return divider_ro_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
380 					     divider->width, divider->flags,  in clk_divider_round_rate()
384 	return divider_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
385 				  divider->width, divider->flags);  in clk_divider_round_rate()
397 		return -EINVAL;  in divider_get_val()
413 	value = divider_get_val(rate, parent_rate, divider->table,  in clk_divider_set_rate()
414 				divider->width, divider->flags);  in clk_divider_set_rate()
418 	if (divider->lock)  in clk_divider_set_rate()
419 		spin_lock_irqsave(divider->lock, flags);  in clk_divider_set_rate()
421 		__acquire(divider->lock);  in clk_divider_set_rate()
423 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {  in clk_divider_set_rate()
424 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in clk_divider_set_rate()
426 		val = clk_readl(divider->reg);  in clk_divider_set_rate()
427 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in clk_divider_set_rate()
429 	val |= (u32)value << divider->shift;  in clk_divider_set_rate()
430 	clk_writel(val, divider->reg);  in clk_divider_set_rate()
432 	if (divider->lock)  in clk_divider_set_rate()
433 		spin_unlock_irqrestore(divider->lock, flags);  in clk_divider_set_rate()
435 		__release(divider->lock);  in clk_divider_set_rate()
453 static struct clk_hw *_register_divider(struct device *dev, const char *name,  in _register_divider()  argument
467 			return ERR_PTR(-EINVAL);  in _register_divider()
474 		return ERR_PTR(-ENOMEM);  in _register_divider()
476 	init.name = name;  in _register_divider()
486 	div->reg = reg;  in _register_divider()
487 	div->shift = shift;  in _register_divider()
488 	div->width = width;  in _register_divider()
489 	div->flags = clk_divider_flags;  in _register_divider()
490 	div->lock = lock;  in _register_divider()
491 	div->hw.init = &init;  in _register_divider()
492 	div->table = table;  in _register_divider()
494 	/* register the clock */  in _register_divider()
495 	hw = &div->hw;  in _register_divider()
506  * clk_register_divider - register a divider clock with the clock framework
507  * @dev: device registering this clock
508  * @name: name of this clock
509  * @parent_name: name of clock's parent
510  * @flags: framework-specific flags
514  * @clk_divider_flags: divider-specific flags for this clock
515  * @lock: shared register lock for this clock
517 struct clk *clk_register_divider(struct device *dev, const char *name,  in clk_register_divider()  argument
524 	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,  in clk_register_divider()
528 	return hw->clk;  in clk_register_divider()
533  * clk_hw_register_divider - register a divider clock with the clock framework
534  * @dev: device registering this clock
535  * @name: name of this clock
536  * @parent_name: name of clock's parent
537  * @flags: framework-specific flags
541  * @clk_divider_flags: divider-specific flags for this clock
542  * @lock: shared register lock for this clock
544 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,  in clk_hw_register_divider()  argument
549 	return _register_divider(dev, name, parent_name, flags, reg, shift,  in clk_hw_register_divider()
555  * clk_register_divider_table - register a table based divider clock with
556  * the clock framework
557  * @dev: device registering this clock
558  * @name: name of this clock
559  * @parent_name: name of clock's parent
560  * @flags: framework-specific flags
564  * @clk_divider_flags: divider-specific flags for this clock
566  * @lock: shared register lock for this clock
568 struct clk *clk_register_divider_table(struct device *dev, const char *name,  in clk_register_divider_table()  argument
576 	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,  in clk_register_divider_table()
580 	return hw->clk;  in clk_register_divider_table()
585  * clk_hw_register_divider_table - register a table based divider clock with
586  * the clock framework
587  * @dev: device registering this clock
588  * @name: name of this clock
589  * @parent_name: name of clock's parent
590  * @flags: framework-specific flags
594  * @clk_divider_flags: divider-specific flags for this clock
596  * @lock: shared register lock for this clock
599 		const char *name, const char *parent_name, unsigned long flags,  in clk_hw_register_divider_table()  argument
604 	return _register_divider(dev, name, parent_name, flags, reg, shift,  in clk_hw_register_divider_table()
626  * clk_hw_unregister_divider - unregister a clk divider
627  * @hw: hardware-specific clock data to unregister