23  * rate - rate is fixed.  clk->rate = parent->rate / div * mult
33 	rate = (unsigned long long int)parent_rate * fix->mult;  in clk_factor_recalc_rate()
46 		best_parent = (rate / fix->mult) * fix->div;  in clk_factor_round_rate()
50 	return (*prate / fix->div) * fix->mult;  in clk_factor_round_rate()
74 		unsigned int mult, unsigned int div)  in clk_hw_register_fixed_factor()  argument
86 	fix->mult = mult;  in clk_hw_register_fixed_factor()
109 		unsigned int mult, unsigned int div)  in clk_register_fixed_factor()  argument
113 	hw = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult,  in clk_register_fixed_factor()
157 	u32 div, mult;  in _of_fixed_factor_clk_setup()  local
166 	if (of_property_read_u32(node, "clock-mult", &mult)) {  in _of_fixed_factor_clk_setup()
167 		pr_err("%s Fixed factor clock <%s> must have a clock-mult property\n",  in _of_fixed_factor_clk_setup()
179 					mult, div);  in _of_fixed_factor_clk_setup()