2  * Copyright 2011-2012 Calxeda, Inc.
21 #include <linux/clk-provider.h>
61 	reg = readl(hbclk->reg);  in clk_pll_prepare()
63 	writel(reg, hbclk->reg);  in clk_pll_prepare()
65 	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)  in clk_pll_prepare()
67 	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)  in clk_pll_prepare()
78 	reg = readl(hbclk->reg);  in clk_pll_unprepare()
80 	writel(reg, hbclk->reg);  in clk_pll_unprepare()
88 	reg = readl(hbclk->reg);  in clk_pll_enable()
90 	writel(reg, hbclk->reg);  in clk_pll_enable()
100 	reg = readl(hbclk->reg);  in clk_pll_disable()
102 	writel(reg, hbclk->reg);  in clk_pll_disable()
111 	reg = readl(hbclk->reg);  in clk_pll_recalc_rate()
140 	divf--;  in clk_pll_calc()
166 	reg = readl(hbclk->reg);  in clk_pll_set_rate()
168 		/* Need to re-lock PLL, so put it into bypass mode */  in clk_pll_set_rate()
170 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
172 		writel(reg | HB_PLL_RESET, hbclk->reg);  in clk_pll_set_rate()
175 		writel(reg | HB_PLL_RESET, hbclk->reg);  in clk_pll_set_rate()
176 		writel(reg, hbclk->reg);  in clk_pll_set_rate()
178 		while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)  in clk_pll_set_rate()
180 		while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)  in clk_pll_set_rate()
185 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
188 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
190 	writel(reg, hbclk->reg);  in clk_pll_set_rate()
209 	u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;  in clk_cpu_periphclk_recalc_rate()
221 	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;  in clk_cpu_a9bclk_recalc_rate()
236 	div = readl(hbclk->reg) & 0x1f;  in clk_periclk_recalc_rate()
263 		return -EINVAL;  in clk_periclk_set_rate()
265 	writel(div >> 1, hbclk->reg);  in clk_periclk_set_rate()
279 	const char *clk_name = node->name;  in hb_clk_init()
294 	srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");  in hb_clk_init()
295 	hb_clk->reg = of_iomap(srnp, 0);  in hb_clk_init()
297 	BUG_ON(!hb_clk->reg);  in hb_clk_init()
298 	hb_clk->reg += reg;  in hb_clk_init()
300 	of_property_read_string(node, "clock-output-names", &clk_name);  in hb_clk_init()
309 	hb_clk->hw.init = &init;  in hb_clk_init()
311 	rc = clk_hw_register(NULL, &hb_clk->hw);  in hb_clk_init()
316 	rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);  in hb_clk_init()
317 	return hb_clk->hw.clk;  in hb_clk_init()
324 CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
330 CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
337 CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
343 CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);