Lines Matching +full:clk +full:- +full:div
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
34 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
39 struct clk *clk; member
44 struct clockgen_pll_div div[8]; member
53 int div; /* PLL_DIVn */ member
82 int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
91 struct clk *sysclk, *coreclk;
93 struct clk *cmux[NUM_CMUX];
94 struct clk *hwaccel[NUM_HWACCEL];
95 struct clk *fman[2];
103 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_out()
113 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_in()
386 reg = ioread32be(&cg->guts->rcwsr[7]); in p2041_init_periph()
389 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
391 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
398 reg = ioread32be(&cg->guts->rcwsr[7]); in p4080_init_periph()
401 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
403 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
406 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
408 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
414 int div = PLL_DIV2; in p5020_init_periph() local
416 reg = ioread32be(&cg->guts->rcwsr[7]); in p5020_init_periph()
418 div = PLL_DIV4; in p5020_init_periph()
421 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
423 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
429 int div = PLL_DIV2; in p5040_init_periph() local
431 reg = ioread32be(&cg->guts->rcwsr[7]); in p5040_init_periph()
433 div = PLL_DIV4; in p5040_init_periph()
436 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
438 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
441 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
443 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
448 cg->fman[0] = cg->hwaccel[1]; in t1023_init_periph()
453 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; in t1040_init_periph()
458 cg->fman[0] = cg->hwaccel[0]; in t2080_init_periph()
463 cg->fman[0] = cg->hwaccel[3]; in t4240_init_periph()
464 cg->fman[1] = cg->hwaccel[4]; in t4240_init_periph()
469 .compat = "fsl,b4420-clockgen",
470 .guts_compat = "fsl,b4860-device-config",
479 0, 1, 1, 1, -1
485 .compat = "fsl,b4860-clockgen",
486 .guts_compat = "fsl,b4860-device-config",
495 0, 1, 1, 1, -1
501 .compat = "fsl,ls1021a-clockgen",
506 0, -1
511 .compat = "fsl,ls1043a-clockgen",
520 0, -1
526 .compat = "fsl,ls1046a-clockgen",
535 0, -1
541 .compat = "fsl,ls1088a-clockgen",
546 0, 0, -1
552 .compat = "fsl,ls1012a-clockgen",
557 0, -1
562 .compat = "fsl,ls2080a-clockgen",
567 0, 0, 1, 1, -1
573 .compat = "fsl,p2041-clockgen",
574 .guts_compat = "fsl,qoriq-device-config-1.0",
580 0, 0, 1, 1, -1
585 .compat = "fsl,p3041-clockgen",
586 .guts_compat = "fsl,qoriq-device-config-1.0",
592 0, 0, 1, 1, -1
597 .compat = "fsl,p4080-clockgen",
598 .guts_compat = "fsl,qoriq-device-config-1.0",
609 .compat = "fsl,p5020-clockgen",
610 .guts_compat = "fsl,qoriq-device-config-1.0",
616 0, 1, -1
621 .compat = "fsl,p5040-clockgen",
622 .guts_compat = "fsl,p5040-device-config",
628 0, 0, 1, 1, -1
633 .compat = "fsl,t1023-clockgen",
634 .guts_compat = "fsl,t1023-device-config",
643 0, 0, -1
649 .compat = "fsl,t1040-clockgen",
650 .guts_compat = "fsl,t1040-device-config",
656 0, 0, 0, 0, -1
662 .compat = "fsl,t2080-clockgen",
663 .guts_compat = "fsl,t2080-device-config",
672 0, -1
678 .compat = "fsl,t4240-clockgen",
679 .guts_compat = "fsl,t4240-device-config",
688 0, 0, 1, -1
715 if (idx >= hwc->num_parents) in mux_set_parent()
716 return -EINVAL; in mux_set_parent()
718 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
719 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
730 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
732 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
734 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
758 int pll, div; in get_pll_div() local
760 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
763 pll = hwc->info->clksel[idx].pll; in get_pll_div()
764 div = hwc->info->clksel[idx].div; in get_pll_div()
766 return &cg->pll[pll].div[div]; in get_pll_div()
769 static struct clk * __init create_mux_common(struct clockgen *cg, in create_mux_common()
778 struct clk *clk; in create_mux_common() local
779 const struct clockgen_pll_div *div; in create_mux_common() local
789 hwc->clksel_to_parent[i] = -1; in create_mux_common()
791 div = get_pll_div(cg, hwc, i); in create_mux_common()
792 if (!div) in create_mux_common()
795 rate = clk_get_rate(div->clk); in create_mux_common()
797 if (hwc->info->clksel[i].flags & CLKSEL_80PCT && in create_mux_common()
805 parent_names[j] = div->name; in create_mux_common()
806 hwc->parent_to_clksel[j] = i; in create_mux_common()
807 hwc->clksel_to_parent[i] = j; in create_mux_common()
814 init.num_parents = hwc->num_parents = j; in create_mux_common()
816 hwc->hw.init = &init; in create_mux_common()
817 hwc->cg = cg; in create_mux_common()
819 clk = clk_register(NULL, &hwc->hw); in create_mux_common()
820 if (IS_ERR(clk)) { in create_mux_common()
822 PTR_ERR(clk)); in create_mux_common()
827 return clk; in create_mux_common()
830 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) in create_one_cmux()
833 const struct clockgen_pll_div *div; in create_one_cmux() local
842 if (cg->info.flags & CG_VER3) in create_one_cmux()
843 hwc->reg = cg->regs + 0x70000 + 0x20 * idx; in create_one_cmux()
845 hwc->reg = cg->regs + 0x20 * idx; in create_one_cmux()
847 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; in create_one_cmux()
856 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in create_one_cmux()
857 div = get_pll_div(cg, hwc, clksel); in create_one_cmux()
858 if (!div) { in create_one_cmux()
863 max_rate = clk_get_rate(div->clk); in create_one_cmux()
867 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); in create_one_cmux()
869 if (cg->info.flags & CG_CMUX_GE_PLAT) in create_one_cmux()
875 pct80_rate, "cg-cmux%d", idx); in create_one_cmux()
878 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) in create_one_hwaccel()
886 hwc->reg = cg->regs + 0x20 * idx + 0x10; in create_one_hwaccel()
887 hwc->info = cg->info.hwaccel[idx]; in create_one_hwaccel()
890 "cg-hwaccel%d", idx); in create_one_hwaccel()
897 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { in create_muxes()
898 if (cg->info.cmux_to_group[i] < 0) in create_muxes()
900 if (cg->info.cmux_to_group[i] >= in create_muxes()
901 ARRAY_SIZE(cg->info.cmux_groups)) { in create_muxes()
906 cg->cmux[i] = create_one_cmux(cg, i); in create_muxes()
909 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { in create_muxes()
910 if (!cg->info.hwaccel[i]) in create_muxes()
913 cg->hwaccel[i] = create_one_hwaccel(cg, i); in create_muxes()
922 * contain a "clocks" property -- otherwise the input clocks may
934 struct clk *clk; in core_mux_init() local
944 clk = clockgen.cmux[idx]; in core_mux_init()
946 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); in core_mux_init()
948 pr_err("%s: Couldn't register clk provider for node %s: %d\n", in core_mux_init()
949 __func__, np->name, rc); in core_mux_init()
954 static struct clk __init
959 if (of_property_read_u32(node, "clock-frequency", &rate)) in sysclk_from_fixed()
960 return ERR_PTR(-ENODEV); in sysclk_from_fixed()
965 static struct clk __init *input_clock(const char *name, struct clk *clk) in input_clock() argument
970 input_name = __clk_get_name(clk); in input_clock()
971 clk = clk_register_fixed_factor(NULL, name, input_name, in input_clock()
973 if (IS_ERR(clk)) in input_clock()
975 PTR_ERR(clk)); in input_clock()
977 return clk; in input_clock()
980 static struct clk __init *input_clock_by_name(const char *name, in input_clock_by_name()
983 struct clk *clk; in input_clock_by_name() local
985 clk = of_clk_get_by_name(clockgen.node, dtname); in input_clock_by_name()
986 if (IS_ERR(clk)) in input_clock_by_name()
987 return clk; in input_clock_by_name()
989 return input_clock(name, clk); in input_clock_by_name()
992 static struct clk __init *input_clock_by_index(const char *name, int idx) in input_clock_by_index()
994 struct clk *clk; in input_clock_by_index() local
996 clk = of_clk_get(clockgen.node, 0); in input_clock_by_index()
997 if (IS_ERR(clk)) in input_clock_by_index()
998 return clk; in input_clock_by_index()
1000 return input_clock(name, clk); in input_clock_by_index()
1003 static struct clk * __init create_sysclk(const char *name) in create_sysclk()
1006 struct clk *clk; in create_sysclk() local
1008 clk = sysclk_from_fixed(clockgen.node, name); in create_sysclk()
1009 if (!IS_ERR(clk)) in create_sysclk()
1010 return clk; in create_sysclk()
1012 clk = input_clock_by_name(name, "sysclk"); in create_sysclk()
1013 if (!IS_ERR(clk)) in create_sysclk()
1014 return clk; in create_sysclk()
1016 clk = input_clock_by_index(name, 0); in create_sysclk()
1017 if (!IS_ERR(clk)) in create_sysclk()
1018 return clk; in create_sysclk()
1022 clk = sysclk_from_fixed(sysclk, name); in create_sysclk()
1023 if (!IS_ERR(clk)) in create_sysclk()
1024 return clk; in create_sysclk()
1031 static struct clk * __init create_coreclk(const char *name) in create_coreclk()
1033 struct clk *clk; in create_coreclk() local
1035 clk = input_clock_by_name(name, "coreclk"); in create_coreclk()
1036 if (!IS_ERR(clk)) in create_coreclk()
1037 return clk; in create_coreclk()
1045 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER)) in create_coreclk()
1046 return clk; in create_coreclk()
1054 struct clk *clk; in sysclk_init() local
1058 clk = clockgen.sysclk; in sysclk_init()
1059 if (clk) in sysclk_init()
1060 of_clk_add_provider(node, of_clk_src_simple_get, clk); in sysclk_init()
1069 struct clockgen_pll *pll = &cg->pll[idx]; in create_one_pll()
1070 const char *input = "cg-sysclk"; in create_one_pll()
1073 if (!(cg->info.pll_mask & (1 << idx))) in create_one_pll()
1076 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1077 if (IS_ERR(cg->coreclk)) in create_one_pll()
1080 input = "cg-coreclk"; in create_one_pll()
1083 if (cg->info.flags & CG_VER3) { in create_one_pll()
1086 reg = cg->regs + 0x60080; in create_one_pll()
1089 reg = cg->regs + 0x80; in create_one_pll()
1092 reg = cg->regs + 0xa0; in create_one_pll()
1095 reg = cg->regs + 0x10080; in create_one_pll()
1098 reg = cg->regs + 0x100a0; in create_one_pll()
1106 reg = cg->regs + 0xc00; in create_one_pll()
1108 reg = cg->regs + 0x800 + 0x20 * (idx - 1); in create_one_pll()
1120 if ((cg->info.flags & CG_VER3) || in create_one_pll()
1121 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) in create_one_pll()
1126 for (i = 0; i < ARRAY_SIZE(pll->div); i++) { in create_one_pll()
1127 struct clk *clk; in create_one_pll() local
1137 snprintf(pll->div[i].name, sizeof(pll->div[i].name), in create_one_pll()
1138 "cg-pll%d-div%d", idx, i + 1); in create_one_pll()
1140 clk = clk_register_fixed_factor(NULL, in create_one_pll()
1141 pll->div[i].name, input, 0, mult, i + 1); in create_one_pll()
1142 if (IS_ERR(clk)) { in create_one_pll()
1144 __func__, pll->div[i].name, PTR_ERR(clk)); in create_one_pll()
1148 pll->div[i].clk = clk; in create_one_pll()
1149 ret = clk_register_clkdev(clk, pll->div[i].name, NULL); in create_one_pll()
1152 __func__, pll->div[i].name, PTR_ERR(clk)); in create_one_pll()
1161 for (i = 0; i < ARRAY_SIZE(cg->pll); i++) in create_plls()
1169 struct clk **subclks; in legacy_pll_init()
1175 count = of_property_count_strings(np, "clock-output-names"); in legacy_pll_init()
1177 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4); in legacy_pll_init()
1178 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL); in legacy_pll_init()
1187 subclks[0] = pll->div[0].clk; in legacy_pll_init()
1188 subclks[1] = pll->div[1].clk; in legacy_pll_init()
1189 subclks[2] = pll->div[3].clk; in legacy_pll_init()
1191 subclks[0] = pll->div[0].clk; in legacy_pll_init()
1192 subclks[1] = pll->div[1].clk; in legacy_pll_init()
1193 subclks[2] = pll->div[2].clk; in legacy_pll_init()
1194 subclks[3] = pll->div[3].clk; in legacy_pll_init()
1197 onecell_data->clks = subclks; in legacy_pll_init()
1198 onecell_data->clk_num = count; in legacy_pll_init()
1202 pr_err("%s: Couldn't register clk provider for node %s: %d\n", in legacy_pll_init()
1203 __func__, np->name, rc); in legacy_pll_init()
1241 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) in clockgen_clk_get()
1244 struct clk *clk; in clockgen_clk_get() local
1248 if (clkspec->args_count < 2) { in clockgen_clk_get()
1250 return ERR_PTR(-EINVAL); in clockgen_clk_get()
1253 type = clkspec->args[0]; in clockgen_clk_get()
1254 idx = clkspec->args[1]; in clockgen_clk_get()
1260 clk = cg->sysclk; in clockgen_clk_get()
1263 if (idx >= ARRAY_SIZE(cg->cmux)) in clockgen_clk_get()
1265 clk = cg->cmux[idx]; in clockgen_clk_get()
1268 if (idx >= ARRAY_SIZE(cg->hwaccel)) in clockgen_clk_get()
1270 clk = cg->hwaccel[idx]; in clockgen_clk_get()
1273 if (idx >= ARRAY_SIZE(cg->fman)) in clockgen_clk_get()
1275 clk = cg->fman[idx]; in clockgen_clk_get()
1278 pll = &cg->pll[PLATFORM_PLL]; in clockgen_clk_get()
1279 if (idx >= ARRAY_SIZE(pll->div)) in clockgen_clk_get()
1281 clk = pll->div[idx].clk; in clockgen_clk_get()
1286 clk = cg->coreclk; in clockgen_clk_get()
1287 if (IS_ERR(clk)) in clockgen_clk_get()
1288 clk = NULL; in clockgen_clk_get()
1294 if (!clk) in clockgen_clk_get()
1295 return ERR_PTR(-ENOENT); in clockgen_clk_get()
1296 return clk; in clockgen_clk_get()
1300 return ERR_PTR(-EINVAL); in clockgen_clk_get()
1363 pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name); in clockgen_init()
1371 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen")) in clockgen_init()
1400 clockgen.sysclk = create_sysclk("cg-sysclk"); in clockgen_init()
1401 clockgen.coreclk = create_coreclk("cg-coreclk"); in clockgen_init()
1410 pr_err("%s: Couldn't register clk provider for node %s: %d\n", in clockgen_init()
1411 __func__, np->name, ret); in clockgen_init()
1420 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1421 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1422 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1423 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1424 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1425 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1426 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1427 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1430 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1431 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1432 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1433 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1434 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1435 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1436 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1437 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);