Lines Matching +full:stm32f469 +full:- +full:qspi
4 * Inspired by clk-asm9260.c .
19 #include <linux/clk-provider.h>
36 #include <dt-bindings/clock/stm32fx-clock.h>
53 #define NONE -1
179 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
261 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
335 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
352 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
364 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
404 return ERR_PTR(-ENOMEM); in clk_register_apb_mul()
406 am->bit_idx = bit_idx; in clk_register_apb_mul()
407 am->hw.init = &init; in clk_register_apb_mul()
415 clk = clk_register(dev, &am->hw); in clk_register_apb_mul()
477 { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
478 { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
488 { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
491 { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
494 { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
520 { PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } },
521 { PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } },
525 { PLL, 50, { "pll", "pll-q", "pll-r" } },
526 { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
527 { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
550 bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); in stm32f4_pll_enable()
552 } while (bit_status && --timeout); in stm32f4_pll_enable()
569 n = (readl(base + pll->offset) >> 6) & 0x1ff; in stm32f4_pll_recalc()
583 if (n < pll->n_start) in stm32f4_pll_round_rate()
584 n = pll->n_start; in stm32f4_pll_round_rate()
608 val = readl(base + pll->offset) & ~(0x1ff << 6); in stm32f4_pll_set_rate()
610 writel(val | ((n & 0x1ff) << 6), base + pll->offset); in stm32f4_pll_set_rate()
654 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
657 stm32f4_pll_disable(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
662 stm32f4_pll_enable(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
687 return ERR_PTR(-ENOMEM); in clk_register_pll_div()
696 pll_div->div.reg = reg; in clk_register_pll_div()
697 pll_div->div.shift = shift; in clk_register_pll_div()
698 pll_div->div.width = width; in clk_register_pll_div()
699 pll_div->div.flags = clk_divider_flags; in clk_register_pll_div()
700 pll_div->div.lock = lock; in clk_register_pll_div()
701 pll_div->div.table = table; in clk_register_pll_div()
702 pll_div->div.hw.init = &init; in clk_register_pll_div()
704 pll_div->hw_pll = pll_hw; in clk_register_pll_div()
707 hw = &pll_div->div.hw; in clk_register_pll_div()
731 return ERR_PTR(-ENOMEM); in stm32f4_rcc_register_pll()
733 vco = &vco_data[data->pll_num]; in stm32f4_rcc_register_pll()
735 init.name = vco->vco_name; in stm32f4_rcc_register_pll()
741 pll->gate.lock = lock; in stm32f4_rcc_register_pll()
742 pll->gate.reg = base + STM32F4_RCC_CR; in stm32f4_rcc_register_pll()
743 pll->gate.bit_idx = vco->bit_idx; in stm32f4_rcc_register_pll()
744 pll->gate.hw.init = &init; in stm32f4_rcc_register_pll()
746 pll->offset = vco->offset; in stm32f4_rcc_register_pll()
747 pll->n_start = data->n_start; in stm32f4_rcc_register_pll()
748 pll->bit_rdy_idx = vco->bit_rdy_idx; in stm32f4_rcc_register_pll()
749 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; in stm32f4_rcc_register_pll()
751 reg = base + pll->offset; in stm32f4_rcc_register_pll()
753 pll_hw = &pll->gate.hw; in stm32f4_rcc_register_pll()
761 if (data->div_name[i]) in stm32f4_rcc_register_pll()
762 clk_register_pll_div(data->div_name[i], in stm32f4_rcc_register_pll()
763 vco->vco_name, in stm32f4_rcc_register_pll()
785 return -EINVAL; in stm32f4_rcc_lookup_clk_idx()
795 return -EINVAL; in stm32f4_rcc_lookup_clk_idx()
801 return stm32fx_end_primary_clk - 1 + hweight64(table[0]) + in stm32f4_rcc_lookup_clk_idx()
809 int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]); in stm32f4_rcc_lookup_clk()
812 return ERR_PTR(-EINVAL); in stm32f4_rcc_lookup_clk()
862 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx)); in rgclk_enable()
866 } while (bit_status && --timeout); in rgclk_enable()
901 return ERR_PTR(-ENOMEM); in clk_register_rgate()
909 rgate->bit_rdy_idx = bit_rdy_idx; in clk_register_rgate()
911 rgate->gate.lock = lock; in clk_register_rgate()
912 rgate->gate.reg = reg; in clk_register_rgate()
913 rgate->gate.bit_idx = bit_idx; in clk_register_rgate()
914 rgate->gate.hw.init = &init; in clk_register_rgate()
916 hw = &rgate->gate.hw; in clk_register_rgate()
995 hw = ERR_PTR(-EINVAL); in stm32_register_cclk()
1002 hw = ERR_PTR(-EINVAL); in stm32_register_cclk()
1006 gate->reg = reg; in stm32_register_cclk()
1007 gate->bit_idx = bit_idx; in stm32_register_cclk()
1008 gate->flags = 0; in stm32_register_cclk()
1009 gate->lock = lock; in stm32_register_cclk()
1011 mux->reg = reg; in stm32_register_cclk()
1012 mux->shift = shift; in stm32_register_cclk()
1013 mux->mask = 3; in stm32_register_cclk()
1014 mux->flags = 0; in stm32_register_cclk()
1017 &mux->hw, &cclk_mux_ops, in stm32_register_cclk()
1019 &gate->hw, &cclk_gate_ops, in stm32_register_cclk()
1048 "no-clock", "lse", "lsi", "hse-rtc"
1051 static const char *dsi_parent[2] = { NULL, "pll-r" };
1053 static const char *lcd_parent[1] = { "pllsai-r-div" };
1055 static const char *i2s_parents[2] = { "plli2s-r", NULL };
1057 static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
1058 "no-clock" };
1060 static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
1066 static const char *spdif_parent[1] = { "plli2s-p" };
1073 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1100 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1112 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1118 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1127 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1139 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1145 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1172 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1208 CLK_HDMI_CEC, "hdmi-cec",
1215 CLK_SPDIF, "spdif-rx",
1348 .compatible = "st,stm32f42xx-rcc",
1352 .compatible = "st,stm32f469-rcc",
1356 .compatible = "st,stm32f746-rcc",
1377 hw = ERR_PTR(-EINVAL); in stm32_register_aux_clk()
1381 gate->reg = base + offset_gate; in stm32_register_aux_clk()
1382 gate->bit_idx = bit_idx; in stm32_register_aux_clk()
1383 gate->flags = 0; in stm32_register_aux_clk()
1384 gate->lock = lock; in stm32_register_aux_clk()
1385 gate_hw = &gate->hw; in stm32_register_aux_clk()
1392 hw = ERR_PTR(-EINVAL); in stm32_register_aux_clk()
1396 mux->reg = base + offset_mux; in stm32_register_aux_clk()
1397 mux->shift = shift; in stm32_register_aux_clk()
1398 mux->mask = mask; in stm32_register_aux_clk()
1399 mux->flags = 0; in stm32_register_aux_clk()
1400 mux_hw = &mux->hw; in stm32_register_aux_clk()
1405 hw = ERR_PTR(-EINVAL); in stm32_register_aux_clk()
1436 pr_err("%s: unable to map resource\n", np->name); in stm32f4_rcc_init()
1450 data = match->data; in stm32f4_rcc_init()
1452 stm32fx_end_primary_clk = data->end_primary; in stm32f4_rcc_init()
1454 clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk, in stm32f4_rcc_init()
1459 stm32f4_gate_map = data->gates_map; in stm32f4_rcc_init()
1479 stm32f4_rcc_register_pll("vco_in", &data->pll_data[0], in stm32f4_rcc_init()
1483 &data->pll_data[1], &stm32f4_clk_lock); in stm32f4_rcc_init()
1486 &data->pll_data[2], &stm32f4_clk_lock); in stm32f4_rcc_init()
1494 hw = clk_register_pll_div(post_div->name, in stm32f4_rcc_init()
1495 post_div->parent, in stm32f4_rcc_init()
1496 post_div->flag, in stm32f4_rcc_init()
1497 base + post_div->offset, in stm32f4_rcc_init()
1498 post_div->shift, in stm32f4_rcc_init()
1499 post_div->width, in stm32f4_rcc_init()
1500 post_div->flag_div, in stm32f4_rcc_init()
1501 post_div->div_table, in stm32f4_rcc_init()
1502 clks[post_div->pll_num], in stm32f4_rcc_init()
1505 if (post_div->idx != NO_IDX) in stm32f4_rcc_init()
1506 clks[post_div->idx] = hw; in stm32f4_rcc_init()
1536 for (n = 0; n < data->gates_num; n++) { in stm32f4_rcc_init()
1541 gd = &data->gates_data[n]; in stm32f4_rcc_init()
1542 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + in stm32f4_rcc_init()
1543 gd->bit_idx; in stm32f4_rcc_init()
1550 NULL, gd->name, gd->parent_name, gd->flags, in stm32f4_rcc_init()
1551 base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock); in stm32f4_rcc_init()
1555 np, gd->name); in stm32f4_rcc_init()
1560 clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0, in stm32f4_rcc_init()
1568 clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0, in stm32f4_rcc_init()
1576 clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse", in stm32f4_rcc_init()
1581 pr_err("Unable to register hse-rtc clock\n"); in stm32f4_rcc_init()
1593 for (n = 0; n < data->aux_clk_num; n++) { in stm32f4_rcc_init()
1597 aux_clk = &data->aux_clk[n]; in stm32f4_rcc_init()
1599 hw = stm32_register_aux_clk(aux_clk->name, in stm32f4_rcc_init()
1600 aux_clk->parent_names, aux_clk->num_parents, in stm32f4_rcc_init()
1601 aux_clk->offset_mux, aux_clk->shift, in stm32f4_rcc_init()
1602 aux_clk->mask, aux_clk->offset_gate, in stm32f4_rcc_init()
1603 aux_clk->bit_idx, aux_clk->flags, in stm32f4_rcc_init()
1607 pr_warn("Unable to register %s clk\n", aux_clk->name); in stm32f4_rcc_init()
1611 if (aux_clk->idx != NO_IDX) in stm32f4_rcc_init()
1612 clks[aux_clk->idx] = hw; in stm32f4_rcc_init()
1615 if (of_device_is_compatible(np, "st,stm32f746-rcc")) in stm32f4_rcc_init()
1626 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
1627 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
1628 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);