2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
12 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/imx21-clock.h>
131 	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0");  in mx21_clocks_init()
132 	clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");  in mx21_clocks_init()
133 	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1");  in mx21_clocks_init()
134 	clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");  in mx21_clocks_init()
135 	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2");  in mx21_clocks_init()
136 	clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");  in mx21_clocks_init()
137 	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3");  in mx21_clocks_init()
138 	clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");  in mx21_clocks_init()
139 	clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");  in mx21_clocks_init()
140 	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0");  in mx21_clocks_init()
141 	clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0");  in mx21_clocks_init()
142 	clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0");  in mx21_clocks_init()
143 	clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1");  in mx21_clocks_init()
144 	clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1");  in mx21_clocks_init()
145 	clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2");  in mx21_clocks_init()
146 	clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2");  in mx21_clocks_init()
147 	clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0");  in mx21_clocks_init()
148 	clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");  in mx21_clocks_init()
149 	clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0");  in mx21_clocks_init()
150 	clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0");  in mx21_clocks_init()
151 	clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0");  in mx21_clocks_init()
152 	clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0");  in mx21_clocks_init()
153 	clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma");  in mx21_clocks_init()
154 	clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma");  in mx21_clocks_init()
155 	clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0");  in mx21_clocks_init()
156 	clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0");  in mx21_clocks_init()
174 CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);