1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
8 #include <dt-bindings/clock/imx27-clock.h>
189 	clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");  in mx27_clocks_init()
190 	clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0");  in mx27_clocks_init()
191 	clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");  in mx27_clocks_init()
192 	clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1");  in mx27_clocks_init()
193 	clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");  in mx27_clocks_init()
194 	clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2");  in mx27_clocks_init()
195 	clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");  in mx27_clocks_init()
196 	clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3");  in mx27_clocks_init()
197 	clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");  in mx27_clocks_init()
198 	clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4");  in mx27_clocks_init()
199 	clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5");  in mx27_clocks_init()
200 	clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5");  in mx27_clocks_init()
201 	clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");  in mx27_clocks_init()
202 	clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0");  in mx27_clocks_init()
203 	clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0");  in mx27_clocks_init()
204 	clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0");  in mx27_clocks_init()
205 	clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1");  in mx27_clocks_init()
206 	clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1");  in mx27_clocks_init()
207 	clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2");  in mx27_clocks_init()
208 	clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2");  in mx27_clocks_init()
209 	clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0");  in mx27_clocks_init()
210 	clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0");  in mx27_clocks_init()
211 	clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1");  in mx27_clocks_init()
212 	clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1");  in mx27_clocks_init()
213 	clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2");  in mx27_clocks_init()
214 	clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2");  in mx27_clocks_init()
215 	clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0");  in mx27_clocks_init()
216 	clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");  in mx27_clocks_init()
217 	clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0");  in mx27_clocks_init()
218 	clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0");  in mx27_clocks_init()
219 	clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0");  in mx27_clocks_init()
220 	clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27");  in mx27_clocks_init()
221 	clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27");  in mx27_clocks_init()
222 	clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27");  in mx27_clocks_init()
223 	clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0");  in mx27_clocks_init()
224 	clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0");  in mx27_clocks_init()
225 	clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0");  in mx27_clocks_init()
226 	clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1");  in mx27_clocks_init()
227 	clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1");  in mx27_clocks_init()
228 	clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1");  in mx27_clocks_init()
229 	clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2");  in mx27_clocks_init()
230 	clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2");  in mx27_clocks_init()
231 	clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2");  in mx27_clocks_init()
232 	clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");  in mx27_clocks_init()
233 	clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");  in mx27_clocks_init()
234 	clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0");  in mx27_clocks_init()
235 	clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0");  in mx27_clocks_init()
236 	clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0");  in mx27_clocks_init()
237 	clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma");  in mx27_clocks_init()
238 	clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma");  in mx27_clocks_init()
239 	clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0");  in mx27_clocks_init()
240 	clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0");  in mx27_clocks_init()
241 	clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0");  in mx27_clocks_init()
242 	clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0");  in mx27_clocks_init()
243 	clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1");  in mx27_clocks_init()
245 	clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad");  in mx27_clocks_init()
246 	clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0");  in mx27_clocks_init()
247 	clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0");  in mx27_clocks_init()
248 	clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");  in mx27_clocks_init()
249 	clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");  in mx27_clocks_init()
261 	for_each_compatible_node(refnp, NULL, "fixed-clock") {  in mx27_clocks_init_dt()
262 		if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))  in mx27_clocks_init_dt()
265 		if (!of_property_read_u32(refnp, "clock-frequency", &fref)) {  in mx27_clocks_init_dt()
279 CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);