157 	clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");  in mx31_clocks_init()
158 	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");  in mx31_clocks_init()
159 	clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");  in mx31_clocks_init()
160 	clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");  in mx31_clocks_init()
161 	clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");  in mx31_clocks_init()
163 	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");  in mx31_clocks_init()
164 	clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");  in mx31_clocks_init()
165 	clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");  in mx31_clocks_init()
168 	clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");  in mx31_clocks_init()
169 	clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");  in mx31_clocks_init()
171 	clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");  in mx31_clocks_init()
172 	clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");  in mx31_clocks_init()
173 	clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");  in mx31_clocks_init()
174 	clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");  in mx31_clocks_init()
175 	clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");  in mx31_clocks_init()
176 	clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");  in mx31_clocks_init()
177 	clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");  in mx31_clocks_init()
178 	clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");  in mx31_clocks_init()
179 	clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");  in mx31_clocks_init()
180 	clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");  in mx31_clocks_init()
181 	clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");  in mx31_clocks_init()
182 	clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");  in mx31_clocks_init()
183 	clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");  in mx31_clocks_init()
184 	clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");  in mx31_clocks_init()
185 	/* i.mx31 has the i.mx21 type uart */  in mx31_clocks_init()
186 	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");  in mx31_clocks_init()
187 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");  in mx31_clocks_init()
188 	clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");  in mx31_clocks_init()
189 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");  in mx31_clocks_init()
190 	clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");  in mx31_clocks_init()
191 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");  in mx31_clocks_init()
192 	clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");  in mx31_clocks_init()
193 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");  in mx31_clocks_init()
194 	clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");  in mx31_clocks_init()
195 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");  in mx31_clocks_init()
196 	clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");  in mx31_clocks_init()
197 	clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");  in mx31_clocks_init()
198 	clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");  in mx31_clocks_init()
200 	clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0");  in mx31_clocks_init()
201 	clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1");  in mx31_clocks_init()
202 	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");  in mx31_clocks_init()
203 	clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");  in mx31_clocks_init()
208 	clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");  in mx31_clocks_init()
224 	for_each_compatible_node(osc_np, NULL, "fixed-clock") {  in mx31_clocks_init_dt()
225 		if (!of_device_is_compatible(osc_np, "fsl,imx-osc26m"))  in mx31_clocks_init_dt()
228 		if (!of_property_read_u32(osc_np, "clock-frequency", &fref)) {  in mx31_clocks_init_dt()
245 CLK_OF_DECLARE(imx31_ccm, "fsl,imx31-ccm", mx31_clocks_init_dt);