33  * struct clk_pllv3 - IMX PLL clock version 3
35  * @base:	 base address of PLL registers
36  * @power_bit:	 pll power bit mask
37  * @powerup_set: set power_bit to power up the PLL
41  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
56 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)  in clk_pllv3_wait_lock()  argument
59 	u32 val = readl_relaxed(pll->base) & pll->power_bit;  in clk_pllv3_wait_lock()
61 	/* No need to wait for lock when pll is not powered up */  in clk_pllv3_wait_lock()
62 	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))  in clk_pllv3_wait_lock()
65 	/* Wait for PLL to lock */  in clk_pllv3_wait_lock()
67 		if (readl_relaxed(pll->base) & BM_PLL_LOCK)  in clk_pllv3_wait_lock()
74 	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;  in clk_pllv3_wait_lock()
79 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_prepare()  local
82 	val = readl_relaxed(pll->base);  in clk_pllv3_prepare()
83 	if (pll->powerup_set)  in clk_pllv3_prepare()
84 		val |= pll->power_bit;  in clk_pllv3_prepare()
86 		val &= ~pll->power_bit;  in clk_pllv3_prepare()
87 	writel_relaxed(val, pll->base);  in clk_pllv3_prepare()
89 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_prepare()
94 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_unprepare()  local
97 	val = readl_relaxed(pll->base);  in clk_pllv3_unprepare()
98 	if (pll->powerup_set)  in clk_pllv3_unprepare()
99 		val &= ~pll->power_bit;  in clk_pllv3_unprepare()
101 		val |= pll->power_bit;  in clk_pllv3_unprepare()
102 	writel_relaxed(val, pll->base);  in clk_pllv3_unprepare()
107 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_is_prepared()  local
109 	if (readl_relaxed(pll->base) & BM_PLL_LOCK)  in clk_pllv3_is_prepared()
118 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_recalc_rate()  local
119 	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;  in clk_pllv3_recalc_rate()
136 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_set_rate()  local
146 	val = readl_relaxed(pll->base);  in clk_pllv3_set_rate()
147 	val &= ~(pll->div_mask << pll->div_shift);  in clk_pllv3_set_rate()
148 	val |= (div << pll->div_shift);  in clk_pllv3_set_rate()
149 	writel_relaxed(val, pll->base);  in clk_pllv3_set_rate()
151 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_set_rate()
166 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_sys_recalc_rate()  local
167 	u32 div = readl_relaxed(pll->base) & pll->div_mask;  in clk_pllv3_sys_recalc_rate()
192 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_sys_set_rate()  local
201 	val = readl_relaxed(pll->base);  in clk_pllv3_sys_set_rate()
202 	val &= ~pll->div_mask;  in clk_pllv3_sys_set_rate()
204 	writel_relaxed(val, pll->base);  in clk_pllv3_sys_set_rate()
206 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_sys_set_rate()
221 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_av_recalc_rate()  local
222 	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);  in clk_pllv3_av_recalc_rate()
223 	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);  in clk_pllv3_av_recalc_rate()
224 	u32 div = readl_relaxed(pll->base) & pll->div_mask;  in clk_pllv3_av_recalc_rate()
268 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_av_set_rate()  local
288 	val = readl_relaxed(pll->base);  in clk_pllv3_av_set_rate()
289 	val &= ~pll->div_mask;  in clk_pllv3_av_set_rate()
291 	writel_relaxed(val, pll->base);  in clk_pllv3_av_set_rate()
292 	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);  in clk_pllv3_av_set_rate()
293 	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);  in clk_pllv3_av_set_rate()
295 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_av_set_rate()
352 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_vf610_recalc_rate()  local
355 	mf.mfn = readl_relaxed(pll->base + PLL_VF610_NUM_OFFSET);  in clk_pllv3_vf610_recalc_rate()
356 	mf.mfd = readl_relaxed(pll->base + PLL_VF610_DENOM_OFFSET);  in clk_pllv3_vf610_recalc_rate()
357 	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;  in clk_pllv3_vf610_recalc_rate()
373 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_vf610_set_rate()  local
378 	val = readl_relaxed(pll->base);  in clk_pllv3_vf610_set_rate()
380 		val &= ~pll->div_mask;	/* clear bit for mfi=20 */  in clk_pllv3_vf610_set_rate()
382 		val |= pll->div_mask;	/* set bit for mfi=22 */  in clk_pllv3_vf610_set_rate()
383 	writel_relaxed(val, pll->base);  in clk_pllv3_vf610_set_rate()
385 	writel_relaxed(mf.mfn, pll->base + PLL_VF610_NUM_OFFSET);  in clk_pllv3_vf610_set_rate()
386 	writel_relaxed(mf.mfd, pll->base + PLL_VF610_DENOM_OFFSET);  in clk_pllv3_vf610_set_rate()
388 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_vf610_set_rate()
403 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_enet_recalc_rate()  local
405 	return pll->ref_clock;  in clk_pllv3_enet_recalc_rate()
419 	struct clk_pllv3 *pll;  in imx_clk_pllv3()  local
424 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in imx_clk_pllv3()
425 	if (!pll)  in imx_clk_pllv3()
428 	pll->power_bit = BM_PLL_POWER;  in imx_clk_pllv3()
438 		pll->div_shift = 1;  in imx_clk_pllv3()
441 		pll->powerup_set = true;  in imx_clk_pllv3()
447 		pll->power_bit = IMX7_ENET_PLL_POWER;  in imx_clk_pllv3()
448 		pll->ref_clock = 1000000000;  in imx_clk_pllv3()
452 		pll->ref_clock = 500000000;  in imx_clk_pllv3()
456 		pll->power_bit = IMX7_DDR_PLL_POWER;  in imx_clk_pllv3()
462 	pll->base = base;  in imx_clk_pllv3()
463 	pll->div_mask = div_mask;  in imx_clk_pllv3()
471 	pll->hw.init = &init;  in imx_clk_pllv3()
473 	clk = clk_register(NULL, &pll->hw);  in imx_clk_pllv3()
475 		kfree(pll);  in imx_clk_pllv3()