Lines Matching +full:reg +full:- +full:shift
1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <linux/clk-provider.h>
47 void __iomem *reg, u8 bit_idx, u8 cgr_val,
55 void __iomem *reg, u8 shift, u32 exclusive_mask);
58 void __iomem *reg, u8 idx);
61 void __iomem *reg, u8 shift, u8 width,
64 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
69 void __iomem *reg, u8 shift, u8 width,
72 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
73 u8 shift, u8 width, const char * const *parents,
81 static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, in imx_clk_mux_ldb() argument
82 u8 shift, u8 width, const char * const *parents, in imx_clk_mux_ldb() argument
86 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, in imx_clk_mux_ldb()
87 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); in imx_clk_mux_ldb()
98 void __iomem *reg, u8 shift, u8 width) in imx_clk_divider() argument
101 reg, shift, width, 0, &imx_ccm_lock); in imx_clk_divider()
105 const char *parent, void __iomem *reg, u8 shift, u8 width, in imx_clk_divider_flags() argument
109 reg, shift, width, 0, &imx_ccm_lock); in imx_clk_divider_flags()
113 void __iomem *reg, u8 shift, u8 width) in imx_clk_divider2() argument
117 reg, shift, width, 0, &imx_ccm_lock); in imx_clk_divider2()
121 void __iomem *reg, u8 shift) in imx_clk_gate() argument
123 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate()
124 shift, 0, &imx_ccm_lock); in imx_clk_gate()
128 void __iomem *reg, u8 shift, unsigned long flags) in imx_clk_gate_flags() argument
130 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, in imx_clk_gate_flags()
131 shift, 0, &imx_ccm_lock); in imx_clk_gate_flags()
135 void __iomem *reg, u8 shift) in imx_clk_gate_dis() argument
137 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate_dis()
138 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); in imx_clk_gate_dis()
142 void __iomem *reg, u8 shift) in imx_clk_gate2() argument
144 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2()
145 shift, 0x3, 0, &imx_ccm_lock, NULL); in imx_clk_gate2()
149 void __iomem *reg, u8 shift, unsigned long flags) in imx_clk_gate2_flags() argument
151 return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, in imx_clk_gate2_flags()
152 shift, 0x3, 0, &imx_ccm_lock, NULL); in imx_clk_gate2_flags()
156 const char *parent, void __iomem *reg, u8 shift, in imx_clk_gate2_shared() argument
159 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2_shared()
160 shift, 0x3, 0, &imx_ccm_lock, share_count); in imx_clk_gate2_shared()
164 const char *parent, void __iomem *reg, u8 shift, in imx_clk_gate2_shared2() argument
168 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, in imx_clk_gate2_shared2()
173 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) in imx_clk_gate2_cgr() argument
175 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2_cgr()
176 shift, cgr_val, 0, &imx_ccm_lock, NULL); in imx_clk_gate2_cgr()
180 void __iomem *reg, u8 shift) in imx_clk_gate3() argument
184 reg, shift, 0, &imx_ccm_lock); in imx_clk_gate3()
188 void __iomem *reg, u8 shift) in imx_clk_gate4() argument
192 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); in imx_clk_gate4()
195 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, in imx_clk_mux() argument
196 u8 shift, u8 width, const char * const *parents, in imx_clk_mux() argument
200 CLK_SET_RATE_NO_REPARENT, reg, shift, in imx_clk_mux()
204 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, in imx_clk_mux2() argument
205 u8 shift, u8 width, const char * const *parents, in imx_clk_mux2() argument
210 reg, shift, width, 0, &imx_ccm_lock); in imx_clk_mux2()
214 void __iomem *reg, u8 shift, u8 width, in imx_clk_mux_flags() argument
219 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, in imx_clk_mux_flags()