Lines Matching +full:data +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
13 #include <linux/clk-provider.h>
26 .data = &(struct meson_clk_pll_data){
30 .width = 9,
35 .width = 5,
40 .width = 2,
45 .width = 12,
50 .width = 1,
55 .width = 1,
67 .data = &(struct meson_clk_pll_data){
71 .width = 9,
76 .width = 5,
81 .width = 2,
86 .width = 1,
91 .width = 1,
203 .data = &(struct meson_clk_pll_data){
207 .width = 9,
212 .width = 5,
217 .width = 2,
222 .width = 10,
227 .width = 1,
232 .width = 1,
256 .data = &(struct meson_clk_pll_data){
260 .width = 9,
265 .width = 5,
270 .width = 2,
275 .width = 13,
280 .width = 1,
285 .width = 1,
312 .data = &(struct clk_regmap_gate_data){
337 .data = &(struct clk_regmap_gate_data){
354 * b) CCF has a clock hand-off mechanism to make the sure the
373 .data = &(struct clk_regmap_gate_data){
397 .data = &(struct clk_regmap_gate_data){
421 .data = &(struct clk_regmap_gate_data){
434 .data = &(struct clk_regmap_div_data){
437 .width = 1,
448 .data = &(struct meson_clk_mpll_data){
452 .width = 14,
457 .width = 1,
462 .width = 9,
467 .width = 1,
481 .data = &(struct clk_regmap_gate_data){
495 .data = &(struct meson_clk_mpll_data){
499 .width = 14,
504 .width = 1,
509 .width = 9,
514 .width = 1,
528 .data = &(struct clk_regmap_gate_data){
542 .data = &(struct meson_clk_mpll_data){
546 .width = 14,
551 .width = 1,
556 .width = 9,
561 .width = 1,
566 .width = 1,
580 .data = &(struct clk_regmap_gate_data){
594 .data = &(struct meson_clk_mpll_data){
598 .width = 14,
603 .width = 1,
608 .width = 9,
613 .width = 1,
627 .data = &(struct clk_regmap_gate_data){
662 .data = &(struct meson_clk_pll_data){
666 .width = 9,
671 .width = 5,
676 .width = 2,
681 .width = 2,
686 .width = 12,
691 .width = 1,
696 .width = 1,
711 .data = &(struct clk_regmap_mux_data){
728 .data = &(struct clk_regmap_mux_data){
745 .data = &(struct clk_regmap_gate_data){
760 .data = &(struct clk_regmap_gate_data){
780 .data = &(struct clk_regmap_mux_data){
795 .data = &(struct clk_regmap_div_data){
798 .width = 7,
810 .data = &(struct clk_regmap_gate_data){
836 .data = &(struct clk_regmap_mux_data){
851 .data = &(struct clk_regmap_div_data){
854 .width = 7,
867 .data = &(struct clk_regmap_gate_data){
882 .data = &(struct clk_regmap_mux_data){
897 .data = &(struct clk_regmap_div_data){
900 .width = 7,
913 .data = &(struct clk_regmap_gate_data){
934 .data = &(struct clk_regmap_mux_data){
955 .data = &(struct clk_regmap_div_data){
958 .width = 11,
970 .data = &(struct clk_regmap_gate_data){
1214 { .compatible = "amlogic,axg-clkc" },
1220 struct device *dev = &pdev->dev; in axg_clkc_probe()
1225 map = syscon_node_to_regmap(of_get_parent(dev->of_node)); in axg_clkc_probe()
1233 axg_clk_regmaps[i]->map = map; in axg_clkc_probe()
1254 .name = "axg-clkc",