1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
10 #include "gxbb-aoclk.h"
14  * 32,768KHz clock for low-power suspend mode and CEC.
17  *         ______      | Div1 |-| Cnt1 |       ______
19  * Xtal-->| Gate |---|  ______   ______  X-X--| Gate |-->
21  *                 |   | Div2 |-| Cnt2 |   |
26  * for each divider to set when the switching is done.
67  *  - will use N1 divider only
69  *  - hold M1 cycles of N1 divider then changes to N2
70  *  - hold M2 cycles of N2 divider then changes to N1
80 	regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, &reg0);  in aoclk_cec_32k_recalc_rate()
81 	regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, &reg1);  in aoclk_cec_32k_recalc_rate()
125 	const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,  in aoclk_cec_32k_round_rate()  local
129 	if (!freq)  in aoclk_cec_32k_round_rate()
132 	return freq->target_rate;  in aoclk_cec_32k_round_rate()
143 	const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,  in aoclk_cec_32k_set_rate()  local
148 	if (!freq)  in aoclk_cec_32k_set_rate()
149 		return -EINVAL;  in aoclk_cec_32k_set_rate()
152 	regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,  in aoclk_cec_32k_set_rate()
155 	reg = FIELD_PREP(CLK_CNTL0_N1_MASK, freq->n1 - 1);  in aoclk_cec_32k_set_rate()
156 	if (freq->dualdiv)  in aoclk_cec_32k_set_rate()
158 		       FIELD_PREP(CLK_CNTL0_N2_MASK, freq->n2 - 1);  in aoclk_cec_32k_set_rate()
160 	regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, reg);  in aoclk_cec_32k_set_rate()
162 	reg = FIELD_PREP(CLK_CNTL1_M1_MASK, freq->m1 - 1);  in aoclk_cec_32k_set_rate()
163 	if (freq->dualdiv)  in aoclk_cec_32k_set_rate()
164 		reg |= FIELD_PREP(CLK_CNTL1_M2_MASK, freq->m2 - 1);  in aoclk_cec_32k_set_rate()
166 	regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, reg);  in aoclk_cec_32k_set_rate()
169 	regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,  in aoclk_cec_32k_set_rate()
174 	regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,  in aoclk_cec_32k_set_rate()
177 	regmap_update_bits(cec_32k->regmap, AO_CRT_CLK_CNTL1,  in aoclk_cec_32k_set_rate()
181 	regmap_update_bits(cec_32k->regmap,  in aoclk_cec_32k_set_rate()