Lines Matching +full:0 +full:x25c

16  * Register offsets from the HardKernel[0] data sheet are listed in comment
20  * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
22 #define HHI_GCLK_MPEG0			0x140 /* 0x50 offset in data sheet */
23 #define HHI_GCLK_MPEG1			0x144 /* 0x51 offset in data sheet */
24 #define HHI_GCLK_MPEG2			0x148 /* 0x52 offset in data sheet */
25 #define HHI_GCLK_OTHER			0x150 /* 0x54 offset in data sheet */
26 #define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
27 #define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
28 #define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
29 #define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
30 #define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
31 #define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
32 #define HHI_NAND_CLK_CNTL		0x25c /* 0x97 offset in data sheet */
33 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
34 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
35 #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
41 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
42 #define HHI_MPLL_CNTL2			0x284 /* 0xa1 offset in data sheet */
43 #define HHI_MPLL_CNTL3			0x288 /* 0xa2 offset in data sheet */
44 #define HHI_MPLL_CNTL4			0x28C /* 0xa3 offset in data sheet */
45 #define HHI_MPLL_CNTL5			0x290 /* 0xa4 offset in data sheet */
46 #define HHI_MPLL_CNTL6			0x294 /* 0xa5 offset in data sheet */
47 #define HHI_MPLL_CNTL7			0x298 /* 0xa6 offset in data sheet */
48 #define HHI_MPLL_CNTL8			0x29C /* 0xa7 offset in data sheet */
49 #define HHI_MPLL_CNTL9			0x2A0 /* 0xa8 offset in data sheet */
50 #define HHI_MPLL_CNTL10			0x2A4 /* 0xa9 offset in data sheet */