Lines Matching +full:lpc3220 +full:- +full:adc
8 * http://www.opensource.org/licenses/gpl-license.html
13 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/lpc32xx-clock.h>
289 LPC32XX_CLK_DEFINE(ADC, "adc", 0x0,
398 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_enable()
400 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy) in clk_mask_enable()
401 return -EBUSY; in clk_mask_enable()
403 return regmap_update_bits(clk_regmap, clk->reg, in clk_mask_enable()
404 clk->enable_mask, clk->enable); in clk_mask_enable()
411 regmap_update_bits(clk_regmap, clk->reg, in clk_mask_disable()
412 clk->disable_mask, clk->disable); in clk_mask_disable()
420 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_is_enabled()
422 return ((val & clk->enable_mask) == clk->enable); in clk_mask_is_enabled()
436 regmap_update_bits(clk_regmap, clk->reg, clk->enable, clk->enable); in clk_pll_enable()
439 regmap_read(clk_regmap, clk->reg, &val); in clk_pll_enable()
447 return -ETIMEDOUT; in clk_pll_enable()
454 regmap_update_bits(clk_regmap, clk->reg, clk->enable, 0x0); in clk_pll_disable()
462 regmap_read(clk_regmap, clk->reg, &val); in clk_pll_is_enabled()
464 val &= clk->enable | PLL_CTRL_LOCK; in clk_pll_is_enabled()
465 if (val == (clk->enable | PLL_CTRL_LOCK)) in clk_pll_is_enabled()
485 regmap_read(clk_regmap, clk->reg, &val); in clk_pll_recalc_rate()
490 clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1; in clk_pll_recalc_rate()
491 clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1; in clk_pll_recalc_rate()
492 clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1; in clk_pll_recalc_rate()
495 clk->p_div = 0; in clk_pll_recalc_rate()
496 clk->mode = PLL_DIRECT_BYPASS; in clk_pll_recalc_rate()
500 clk->mode = PLL_BYPASS; in clk_pll_recalc_rate()
501 return parent_rate / (1 << clk->p_div); in clk_pll_recalc_rate()
504 clk->p_div = 0; in clk_pll_recalc_rate()
505 clk->mode = PLL_DIRECT; in clk_pll_recalc_rate()
508 ref_rate = parent_rate / clk->n_div; in clk_pll_recalc_rate()
509 rate = cco_rate = ref_rate * clk->m_div; in clk_pll_recalc_rate()
513 cco_rate *= (1 << clk->p_div); in clk_pll_recalc_rate()
514 clk->mode = PLL_INTEGER; in clk_pll_recalc_rate()
516 rate /= (1 << clk->p_div); in clk_pll_recalc_rate()
517 clk->mode = PLL_NON_INTEGER; in clk_pll_recalc_rate()
524 clk->n_div, clk->m_div, (1 << clk->p_div), rate); in clk_pll_recalc_rate()
545 switch (clk->mode) { in clk_pll_set_rate()
548 val |= (clk->m_div - 1) << 1; in clk_pll_set_rate()
549 val |= (clk->n_div - 1) << 9; in clk_pll_set_rate()
550 new_rate = (parent_rate * clk->m_div) / clk->n_div; in clk_pll_set_rate()
554 val |= (clk->p_div - 1) << 11; in clk_pll_set_rate()
555 new_rate = parent_rate / (1 << (clk->p_div)); in clk_pll_set_rate()
563 val |= (clk->m_div - 1) << 1; in clk_pll_set_rate()
564 val |= (clk->n_div - 1) << 9; in clk_pll_set_rate()
565 val |= (clk->p_div - 1) << 11; in clk_pll_set_rate()
566 new_rate = (parent_rate * clk->m_div) / clk->n_div; in clk_pll_set_rate()
570 val |= (clk->m_div - 1) << 1; in clk_pll_set_rate()
571 val |= (clk->n_div - 1) << 9; in clk_pll_set_rate()
572 val |= (clk->p_div - 1) << 11; in clk_pll_set_rate()
573 new_rate = (parent_rate * clk->m_div) / in clk_pll_set_rate()
574 (clk->n_div * (1 << clk->p_div)); in clk_pll_set_rate()
577 return -EINVAL; in clk_pll_set_rate()
582 return -EINVAL; in clk_pll_set_rate()
584 return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val); in clk_pll_set_rate()
598 return -EINVAL; in clk_hclk_pll_round_rate()
601 for (p_i = 4; p_i >= 0; p_i--) { in clk_hclk_pll_round_rate()
602 for (n_i = 4; n_i > 0; n_i--) { in clk_hclk_pll_round_rate()
613 if (o * n_i * (1 << p_i) - i * m_i <= d) { in clk_hclk_pll_round_rate()
617 d = o * n_i * (1 << p_i) - i * m_i; in clk_hclk_pll_round_rate()
625 return -EINVAL; in clk_hclk_pll_round_rate()
628 clk->m_div = m; in clk_hclk_pll_round_rate()
629 clk->n_div = n; in clk_hclk_pll_round_rate()
630 clk->p_div = p; in clk_hclk_pll_round_rate()
632 /* Set only direct or non-integer mode of PLL */ in clk_hclk_pll_round_rate()
634 clk->mode = PLL_DIRECT; in clk_hclk_pll_round_rate()
636 clk->mode = PLL_NON_INTEGER; in clk_hclk_pll_round_rate()
644 pr_debug("%s: %lu: found closest: %llu/%llu/%llu - %llu\n", in clk_hclk_pll_round_rate()
662 * and post-divider must be 4, this slightly simplifies calculation of in clk_usb_pll_round_rate()
666 return -EINVAL; in clk_usb_pll_round_rate()
671 return -EINVAL; in clk_usb_pll_round_rate()
676 return -EINVAL; in clk_usb_pll_round_rate()
680 for (d_i = 16; d_i >= 1; d_i--) { in clk_usb_pll_round_rate()
689 clk->n_div = n_i; in clk_usb_pll_round_rate()
690 clk->m_div = m; in clk_usb_pll_round_rate()
691 clk->p_div = 2; in clk_usb_pll_round_rate()
692 clk->mode = PLL_NON_INTEGER; in clk_usb_pll_round_rate()
699 return -EINVAL; in clk_usb_pll_round_rate()
723 regmap_read(clk_regmap, clk->reg, &val); in clk_ddram_is_enabled()
724 val &= clk->enable_mask | clk->busy_mask; in clk_ddram_is_enabled()
735 regmap_read(clk_regmap, clk->reg, &val); in clk_ddram_enable()
736 hclk_div = val & clk->busy_mask; in clk_ddram_enable()
744 return -EINVAL; in clk_ddram_enable()
746 return regmap_update_bits(clk_regmap, clk->reg, in clk_ddram_enable()
747 clk->enable_mask, hclk_div << 7); in clk_ddram_enable()
759 regmap_read(clk_regmap, clk->reg, &val); in clk_ddram_recalc_rate()
760 val &= clk->enable_mask; in clk_ddram_recalc_rate()
778 regmap_read(clk_regmap, clk->reg, &val); in lpc32xx_clk_uart_recalc_rate()
807 pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable); in clk_usb_enable()
809 if (clk->ctrl_mask) { in clk_usb_enable()
812 clk->ctrl_mask, clk->ctrl_enable); in clk_usb_enable()
816 if (clk->busy && (val & clk->busy) == clk->busy) { in clk_usb_enable()
817 if (clk->ctrl_mask) in clk_usb_enable()
820 return -EBUSY; in clk_usb_enable()
823 val |= clk->enable; in clk_usb_enable()
828 if ((val & clk->enable) == clk->enable) in clk_usb_enable()
832 if ((val & clk->enable) == clk->enable) in clk_usb_enable()
835 if (clk->ctrl_mask) in clk_usb_enable()
838 return -ETIMEDOUT; in clk_usb_enable()
846 val &= ~clk->enable; in clk_usb_disable()
849 if (clk->ctrl_mask) in clk_usb_disable()
851 clk->ctrl_mask, clk->ctrl_disable); in clk_usb_disable()
859 if (clk->ctrl_mask) { in clk_usb_is_enabled()
861 if ((ctrl_val & clk->ctrl_mask) != clk->ctrl_enable) in clk_usb_is_enabled()
867 return ((val & clk->enable) == clk->enable); in clk_usb_is_enabled()
892 u32 mask = BIT(clk->bit_idx); in lpc32xx_clk_gate_enable()
893 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask); in lpc32xx_clk_gate_enable()
895 return regmap_update_bits(clk_regmap, clk->reg, mask, val); in lpc32xx_clk_gate_enable()
901 u32 mask = BIT(clk->bit_idx); in lpc32xx_clk_gate_disable()
902 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0); in lpc32xx_clk_gate_disable()
904 regmap_update_bits(clk_regmap, clk->reg, mask, val); in lpc32xx_clk_gate_disable()
913 regmap_read(clk_regmap, clk->reg, &val); in lpc32xx_clk_gate_is_enabled()
914 is_set = val & BIT(clk->bit_idx); in lpc32xx_clk_gate_is_enabled()
916 return (clk->flags & CLK_GATE_SET_TO_DISABLE ? !is_set : is_set); in lpc32xx_clk_gate_is_enabled()
925 #define div_mask(width) ((1 << (width)) - 1)
932 for (clkt = table; clkt->div; clkt++) in _get_table_div()
933 if (clkt->val == val) in _get_table_div()
934 return clkt->div; in _get_table_div()
954 regmap_read(clk_regmap, divider->reg, &val); in clk_divider_recalc_rate()
956 val >>= divider->shift; in clk_divider_recalc_rate()
957 val &= div_mask(divider->width); in clk_divider_recalc_rate()
959 return divider_recalc_rate(hw, parent_rate, val, divider->table, in clk_divider_recalc_rate()
960 divider->flags, divider->width); in clk_divider_recalc_rate()
970 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in clk_divider_round_rate()
971 regmap_read(clk_regmap, divider->reg, &bestdiv); in clk_divider_round_rate()
972 bestdiv >>= divider->shift; in clk_divider_round_rate()
973 bestdiv &= div_mask(divider->width); in clk_divider_round_rate()
974 bestdiv = _get_div(divider->table, bestdiv, divider->flags, in clk_divider_round_rate()
975 divider->width); in clk_divider_round_rate()
979 return divider_round_rate(hw, rate, prate, divider->table, in clk_divider_round_rate()
980 divider->width, divider->flags); in clk_divider_round_rate()
989 value = divider_get_val(rate, parent_rate, divider->table, in clk_divider_set_rate()
990 divider->width, divider->flags); in clk_divider_set_rate()
992 return regmap_update_bits(clk_regmap, divider->reg, in clk_divider_set_rate()
993 div_mask(divider->width) << divider->shift, in clk_divider_set_rate()
994 value << divider->shift); in clk_divider_set_rate()
1009 regmap_read(clk_regmap, mux->reg, &val); in clk_mux_get_parent()
1010 val >>= mux->shift; in clk_mux_get_parent()
1011 val &= mux->mask; in clk_mux_get_parent()
1013 if (mux->table) { in clk_mux_get_parent()
1017 if (mux->table[i] == val) in clk_mux_get_parent()
1019 return -EINVAL; in clk_mux_get_parent()
1023 return -EINVAL; in clk_mux_get_parent()
1032 if (mux->table) in clk_mux_set_parent()
1033 index = mux->table[index]; in clk_mux_set_parent()
1035 return regmap_update_bits(clk_regmap, mux->reg, in clk_mux_set_parent()
1036 mux->mask << mux->shift, index << mux->shift); in clk_mux_set_parent()
1240 /* Register 3 read-only muxes with a single control PWR_CTRL[2] */
1247 /* Register 2 read-only muxes with a single control PWR_CTRL[10] */
1359 * ADC/TS clock unfortunately cannot be registered as a composite one
1363 * rtc-->[gate]-->| |
1364 * | mux |--> adc/ts
1365 * pclk-->[div]-->| |
1368 * ADC --- resulting clock must be <= 4.5 MHz
1369 * TS --- resulting clock must be <= 400 KHz
1373 LPC32XX_DEFINE_MUX(ADC, ADCCLK_CTRL1, 8, 0x1, NULL, 0),
1396 for (i = 0; i < lpc32xx_clk->num_parents; i++) in lpc32xx_clk_register()
1397 parents[i] = clk_proto[lpc32xx_clk->parents[i]].name; in lpc32xx_clk_register()
1399 pr_debug("%s: derived from '%s', clock type %d\n", lpc32xx_clk->name, in lpc32xx_clk_register()
1400 parents[0], clk_hw->type); in lpc32xx_clk_register()
1402 switch (clk_hw->type) { in lpc32xx_clk_register()
1411 .name = lpc32xx_clk->name, in lpc32xx_clk_register()
1413 .num_parents = lpc32xx_clk->num_parents, in lpc32xx_clk_register()
1414 .flags = lpc32xx_clk->flags, in lpc32xx_clk_register()
1415 .ops = clk_hw->hw0.ops, in lpc32xx_clk_register()
1419 if (clk_hw->type == CLK_LPC32XX) in lpc32xx_clk_register()
1420 hw = &clk_hw->hw0.clk.hw; in lpc32xx_clk_register()
1421 else if (clk_hw->type == CLK_LPC32XX_PLL) in lpc32xx_clk_register()
1422 hw = &clk_hw->hw0.pll.hw; in lpc32xx_clk_register()
1423 else if (clk_hw->type == CLK_LPC32XX_USB) in lpc32xx_clk_register()
1424 hw = &clk_hw->hw0.usb_clk.hw; in lpc32xx_clk_register()
1425 else if (clk_hw->type == CLK_MUX) in lpc32xx_clk_register()
1426 hw = &clk_hw->hw0.mux.hw; in lpc32xx_clk_register()
1427 else if (clk_hw->type == CLK_DIV) in lpc32xx_clk_register()
1428 hw = &clk_hw->hw0.div.hw; in lpc32xx_clk_register()
1429 else if (clk_hw->type == CLK_GATE) in lpc32xx_clk_register()
1430 hw = &clk_hw->hw0.gate.hw; in lpc32xx_clk_register()
1432 return ERR_PTR(-EINVAL); in lpc32xx_clk_register()
1434 hw->init = &clk_init; in lpc32xx_clk_register()
1444 mux0 = clk_hw->hw1.mux; in lpc32xx_clk_register()
1445 div0 = clk_hw->hw1.div; in lpc32xx_clk_register()
1446 gate0 = clk_hw->hw1.gate; in lpc32xx_clk_register()
1448 mops = mux0->ops; in lpc32xx_clk_register()
1449 mux_hw = &mux0->clk.hw; in lpc32xx_clk_register()
1452 dops = div0->ops; in lpc32xx_clk_register()
1453 div_hw = &div0->clk.hw; in lpc32xx_clk_register()
1456 gops = gate0->ops; in lpc32xx_clk_register()
1457 gate_hw = &gate0->clk.hw; in lpc32xx_clk_register()
1460 clk = clk_register_composite(NULL, lpc32xx_clk->name, in lpc32xx_clk_register()
1461 parents, lpc32xx_clk->num_parents, in lpc32xx_clk_register()
1463 gate_hw, gops, lpc32xx_clk->flags); in lpc32xx_clk_register()
1468 struct clk_fixed_rate *fixed = &clk_hw->f; in lpc32xx_clk_register()
1470 clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name, in lpc32xx_clk_register()
1471 parents[0], fixed->flags, fixed->fixed_rate); in lpc32xx_clk_register()
1475 clk = ERR_PTR(-EINVAL); in lpc32xx_clk_register()
1570 CLK_OF_DECLARE(lpc32xx_clk, "nxp,lpc3220-clk", lpc32xx_clk_init);
1593 CLK_OF_DECLARE(lpc32xx_usb_clk, "nxp,lpc3220-usb-clk", lpc32xx_usb_clk_init);