18 #include <linux/delay.h>
20 #include <linux/clk-provider.h>
25 #include "clk-pll.h"
39 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_enable()
48 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,  in clk_pll_enable()
54 	 * H/W requires a 5us delay between disabling the bypass and  in clk_pll_enable()
55 	 * de-asserting the reset. Delay 10us just to be safe.  in clk_pll_enable()
59 	/* De-assert active-low PLL reset. */  in clk_pll_enable()
60 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,  in clk_pll_enable()
69 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,  in clk_pll_enable()
79 	regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_disable()
84 	regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);  in clk_pll_disable()
95 	regmap_read(pll->clkr.regmap, pll->l_reg, &l);  in clk_pll_recalc_rate()
96 	regmap_read(pll->clkr.regmap, pll->m_reg, &m);  in clk_pll_recalc_rate()
97 	regmap_read(pll->clkr.regmap, pll->n_reg, &n);  in clk_pll_recalc_rate()
110 	if (pll->post_div_width) {  in clk_pll_recalc_rate()
111 		regmap_read(pll->clkr.regmap, pll->config_reg, &config);  in clk_pll_recalc_rate()
112 		config >>= pll->post_div_shift;  in clk_pll_recalc_rate()
113 		config &= BIT(pll->post_div_width) - 1;  in clk_pll_recalc_rate()
126 	for (; f->freq; f++)  in find_freq()
127 		if (rate <= f->freq)  in find_freq()
139 	f = find_freq(pll->freq_tbl, req->rate);  in clk_pll_determine_rate()
141 		req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate);  in clk_pll_determine_rate()
143 		req->rate = f->freq;  in clk_pll_determine_rate()
157 	f = find_freq(pll->freq_tbl, rate);  in clk_pll_set_rate()
159 		return -EINVAL;  in clk_pll_set_rate()
161 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_set_rate()
167 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);  in clk_pll_set_rate()
168 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);  in clk_pll_set_rate()
169 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);  in clk_pll_set_rate()
170 	regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);  in clk_pll_set_rate()
192 	const char *name = clk_hw_get_name(&pll->clkr.hw);  in wait_for_pll()
195 	for (count = 200; count > 0; count--) {  in wait_for_pll()
196 		ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);  in wait_for_pll()
199 		if (val & BIT(pll->status_bit))  in wait_for_pll()
205 	return -ETIMEDOUT;  in wait_for_pll()
232 	regmap_write(regmap, pll->l_reg, config->l);  in clk_pll_configure()
233 	regmap_write(regmap, pll->m_reg, config->m);  in clk_pll_configure()
234 	regmap_write(regmap, pll->n_reg, config->n);  in clk_pll_configure()
236 	val = config->vco_val;  in clk_pll_configure()
237 	val |= config->pre_div_val;  in clk_pll_configure()
238 	val |= config->post_div_val;  in clk_pll_configure()
239 	val |= config->mn_ena_mask;  in clk_pll_configure()
240 	val |= config->main_output_mask;  in clk_pll_configure()
241 	val |= config->aux_output_mask;  in clk_pll_configure()
243 	mask = config->vco_mask;  in clk_pll_configure()
244 	mask |= config->pre_div_mask;  in clk_pll_configure()
245 	mask |= config->post_div_mask;  in clk_pll_configure()
246 	mask |= config->mn_ena_mask;  in clk_pll_configure()
247 	mask |= config->main_output_mask;  in clk_pll_configure()
248 	mask |= config->aux_output_mask;  in clk_pll_configure()
250 	regmap_update_bits(regmap, pll->config_reg, mask, val);  in clk_pll_configure()
258 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);  in clk_pll_configure_sr()
267 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);  in clk_pll_configure_sr_hpm_lp()
277 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_sr2_enable()
282 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,  in clk_pll_sr2_enable()
288 	 * H/W requires a 5us delay between disabling the bypass and  in clk_pll_sr2_enable()
289 	 * de-asserting the reset. Delay 10us just to be safe.  in clk_pll_sr2_enable()
293 	/* De-assert active-low PLL reset. */  in clk_pll_sr2_enable()
294 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,  in clk_pll_sr2_enable()
304 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,  in clk_pll_sr2_enable()
317 	f = find_freq(pll->freq_tbl, rate);  in clk_pll_sr2_set_rate()
319 		return -EINVAL;  in clk_pll_sr2_set_rate()
321 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_sr2_set_rate()
327 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);  in clk_pll_sr2_set_rate()
328 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);  in clk_pll_sr2_set_rate()
329 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);  in clk_pll_sr2_set_rate()