Lines Matching +full:bank +full:- +full:width
18 #include <linux/clk-provider.h>
23 #include "clk-rcg.h"
28 ns >>= s->src_sel_shift; in ns_to_src()
38 mask <<= s->src_sel_shift; in src_to_ns()
41 ns |= src << s->src_sel_shift; in src_to_ns()
52 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_get_parent()
55 ns = ns_to_src(&rcg->s, ns); in clk_rcg_get_parent()
57 if (ns == rcg->s.parent_map[i].cfg) in clk_rcg_get_parent()
66 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) in reg_to_bank() argument
68 bank &= BIT(rcg->mux_sel_bit); in reg_to_bank()
69 return !!bank; in reg_to_bank()
77 int bank; in clk_dyn_rcg_get_parent() local
81 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in clk_dyn_rcg_get_parent()
84 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_get_parent()
85 s = &rcg->s[bank]; in clk_dyn_rcg_get_parent()
87 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); in clk_dyn_rcg_get_parent()
93 if (ns == s->parent_map[i].cfg) in clk_dyn_rcg_get_parent()
107 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_set_parent()
108 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns); in clk_rcg_set_parent()
109 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); in clk_rcg_set_parent()
116 md >>= mn->m_val_shift; in md_to_m()
117 md &= BIT(mn->width) - 1; in md_to_m()
123 ns >>= p->pre_div_shift; in ns_to_pre_div()
124 ns &= BIT(p->pre_div_width) - 1; in ns_to_pre_div()
132 mask = BIT(p->pre_div_width) - 1; in pre_div_to_ns()
133 mask <<= p->pre_div_shift; in pre_div_to_ns()
136 ns |= pre_div << p->pre_div_shift; in pre_div_to_ns()
144 mask_w = BIT(mn->width) - 1; in mn_to_md()
145 mask = (mask_w << mn->m_val_shift) | mask_w; in mn_to_md()
149 m <<= mn->m_val_shift; in mn_to_md()
159 ns = ~ns >> mn->n_val_shift; in ns_m_to_n()
160 ns &= BIT(mn->width) - 1; in ns_m_to_n()
166 val >>= mn->mnctr_mode_shift; in reg_to_mnctr_mode()
175 mask = BIT(mn->width) - 1; in mn_to_ns()
176 mask <<= mn->n_val_shift; in mn_to_ns()
180 n = n - m; in mn_to_ns()
182 n &= BIT(mn->width) - 1; in mn_to_ns()
183 n <<= mn->n_val_shift; in mn_to_ns()
194 mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift; in mn_to_reg()
195 mask |= BIT(mn->mnctr_en_bit); in mn_to_reg()
199 val |= BIT(mn->mnctr_en_bit); in mn_to_reg()
200 val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift; in mn_to_reg()
209 int bank, new_bank, ret, index; in configure_bank() local
215 bool banked_mn = !!rcg->mn[1].width; in configure_bank()
216 bool banked_p = !!rcg->p[1].pre_div_width; in configure_bank()
217 struct clk_hw *hw = &rcg->clkr.hw; in configure_bank()
219 enabled = __clk_is_enabled(hw->clk); in configure_bank()
221 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in configure_bank()
224 bank = reg_to_bank(rcg, reg); in configure_bank()
225 new_bank = enabled ? !bank : bank; in configure_bank()
227 ns_reg = rcg->ns_reg[new_bank]; in configure_bank()
228 ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns); in configure_bank()
233 mn = &rcg->mn[new_bank]; in configure_bank()
234 md_reg = rcg->md_reg[new_bank]; in configure_bank()
236 ns |= BIT(mn->mnctr_reset_bit); in configure_bank()
237 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
241 ret = regmap_read(rcg->clkr.regmap, md_reg, &md); in configure_bank()
244 md = mn_to_md(mn, f->m, f->n, md); in configure_bank()
245 ret = regmap_write(rcg->clkr.regmap, md_reg, md); in configure_bank()
248 ns = mn_to_ns(mn, f->m, f->n, ns); in configure_bank()
249 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
254 if (rcg->ns_reg[0] != rcg->ns_reg[1]) { in configure_bank()
255 ns = mn_to_reg(mn, f->m, f->n, ns); in configure_bank()
256 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
260 reg = mn_to_reg(mn, f->m, f->n, reg); in configure_bank()
261 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, in configure_bank()
267 ns &= ~BIT(mn->mnctr_reset_bit); in configure_bank()
268 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
274 p = &rcg->p[new_bank]; in configure_bank()
275 ns = pre_div_to_ns(p, f->pre_div - 1, ns); in configure_bank()
278 s = &rcg->s[new_bank]; in configure_bank()
279 index = qcom_find_src_index(hw, s->parent_map, f->src); in configure_bank()
282 ns = src_to_ns(s, s->parent_map[index].cfg, ns); in configure_bank()
283 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
288 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in configure_bank()
291 reg ^= BIT(rcg->mux_sel_bit); in configure_bank()
292 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg); in configure_bank()
303 int bank; in clk_dyn_rcg_set_parent() local
305 bool banked_mn = !!rcg->mn[1].width; in clk_dyn_rcg_set_parent()
306 bool banked_p = !!rcg->p[1].pre_div_width; in clk_dyn_rcg_set_parent()
308 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in clk_dyn_rcg_set_parent()
309 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_set_parent()
311 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); in clk_dyn_rcg_set_parent()
314 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); in clk_dyn_rcg_set_parent()
315 f.m = md_to_m(&rcg->mn[bank], md); in clk_dyn_rcg_set_parent()
316 f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m); in clk_dyn_rcg_set_parent()
320 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1; in clk_dyn_rcg_set_parent()
322 f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index); in clk_dyn_rcg_set_parent()
330 * rate = ----------- x ---
354 struct mn *mn = &rcg->mn; in clk_rcg_recalc_rate()
356 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_recalc_rate()
357 pre_div = ns_to_pre_div(&rcg->p, ns); in clk_rcg_recalc_rate()
359 if (rcg->mn.width) { in clk_rcg_recalc_rate()
360 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md); in clk_rcg_recalc_rate()
364 if (rcg->clkr.enable_reg != rcg->ns_reg) in clk_rcg_recalc_rate()
365 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode); in clk_rcg_recalc_rate()
379 int bank; in clk_dyn_rcg_recalc_rate() local
381 bool banked_p = !!rcg->p[1].pre_div_width; in clk_dyn_rcg_recalc_rate()
382 bool banked_mn = !!rcg->mn[1].width; in clk_dyn_rcg_recalc_rate()
384 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in clk_dyn_rcg_recalc_rate()
385 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_recalc_rate()
387 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); in clk_dyn_rcg_recalc_rate()
391 mn = &rcg->mn[bank]; in clk_dyn_rcg_recalc_rate()
392 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); in clk_dyn_rcg_recalc_rate()
396 if (rcg->ns_reg[0] != rcg->ns_reg[1]) in clk_dyn_rcg_recalc_rate()
402 pre_div = ns_to_pre_div(&rcg->p[bank], ns); in clk_dyn_rcg_recalc_rate()
411 unsigned long clk_flags, rate = req->rate; in _freq_tbl_determine_rate()
417 return -EINVAL; in _freq_tbl_determine_rate()
419 index = qcom_find_src_index(hw, parent_map, f->src); in _freq_tbl_determine_rate()
426 rate = rate * f->pre_div; in _freq_tbl_determine_rate()
427 if (f->n) { in _freq_tbl_determine_rate()
429 tmp = tmp * f->n; in _freq_tbl_determine_rate()
430 do_div(tmp, f->m); in _freq_tbl_determine_rate()
436 req->best_parent_hw = p; in _freq_tbl_determine_rate()
437 req->best_parent_rate = rate; in _freq_tbl_determine_rate()
438 req->rate = f->freq; in _freq_tbl_determine_rate()
448 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, in clk_rcg_determine_rate()
449 rcg->s.parent_map); in clk_rcg_determine_rate()
457 int bank; in clk_dyn_rcg_determine_rate() local
460 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); in clk_dyn_rcg_determine_rate()
461 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_determine_rate()
462 s = &rcg->s[bank]; in clk_dyn_rcg_determine_rate()
464 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map); in clk_dyn_rcg_determine_rate()
471 const struct freq_tbl *f = rcg->freq_tbl; in clk_rcg_bypass_determine_rate()
473 int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src); in clk_rcg_bypass_determine_rate()
475 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); in clk_rcg_bypass_determine_rate()
476 req->best_parent_rate = clk_hw_round_rate(p, req->rate); in clk_rcg_bypass_determine_rate()
477 req->rate = req->best_parent_rate; in clk_rcg_bypass_determine_rate()
485 struct mn *mn = &rcg->mn; in __clk_rcg_set_rate()
489 if (rcg->mn.reset_in_cc) in __clk_rcg_set_rate()
490 reset_reg = rcg->clkr.enable_reg; in __clk_rcg_set_rate()
492 reset_reg = rcg->ns_reg; in __clk_rcg_set_rate()
494 if (rcg->mn.width) { in __clk_rcg_set_rate()
495 mask = BIT(mn->mnctr_reset_bit); in __clk_rcg_set_rate()
496 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask); in __clk_rcg_set_rate()
498 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md); in __clk_rcg_set_rate()
499 md = mn_to_md(mn, f->m, f->n, md); in __clk_rcg_set_rate()
500 regmap_write(rcg->clkr.regmap, rcg->md_reg, md); in __clk_rcg_set_rate()
502 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in __clk_rcg_set_rate()
504 if (rcg->clkr.enable_reg != rcg->ns_reg) { in __clk_rcg_set_rate()
505 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl); in __clk_rcg_set_rate()
506 ctl = mn_to_reg(mn, f->m, f->n, ctl); in __clk_rcg_set_rate()
507 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl); in __clk_rcg_set_rate()
509 ns = mn_to_reg(mn, f->m, f->n, ns); in __clk_rcg_set_rate()
511 ns = mn_to_ns(mn, f->m, f->n, ns); in __clk_rcg_set_rate()
513 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in __clk_rcg_set_rate()
516 ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns); in __clk_rcg_set_rate()
517 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); in __clk_rcg_set_rate()
519 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0); in __clk_rcg_set_rate()
530 f = qcom_find_freq(rcg->freq_tbl, rate); in clk_rcg_set_rate()
532 return -EINVAL; in clk_rcg_set_rate()
542 return __clk_rcg_set_rate(rcg, rcg->freq_tbl); in clk_rcg_bypass_set_rate()
550 p = req->best_parent_hw; in clk_rcg_bypass2_determine_rate()
551 req->best_parent_rate = clk_hw_round_rate(p, req->rate); in clk_rcg_bypass2_determine_rate()
552 req->rate = req->best_parent_rate; in clk_rcg_bypass2_determine_rate()
565 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_bypass2_set_rate()
569 src = ns_to_src(&rcg->s, ns); in clk_rcg_bypass2_set_rate()
570 f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1; in clk_rcg_bypass2_set_rate()
573 if (src == rcg->s.parent_map[i].cfg) { in clk_rcg_bypass2_set_rate()
574 f.src = rcg->s.parent_map[i].src; in clk_rcg_bypass2_set_rate()
579 return -EINVAL; in clk_rcg_bypass2_set_rate()
608 for (; frac->num; frac++) { in clk_rcg_pixel_determine_rate()
609 request = (req->rate * frac->den) / frac->num; in clk_rcg_pixel_determine_rate()
611 src_rate = clk_hw_round_rate(req->best_parent_hw, request); in clk_rcg_pixel_determine_rate()
613 if ((src_rate < (request - delta)) || in clk_rcg_pixel_determine_rate()
617 req->best_parent_rate = src_rate; in clk_rcg_pixel_determine_rate()
618 req->rate = (src_rate * frac->num) / frac->den; in clk_rcg_pixel_determine_rate()
622 return -EINVAL; in clk_rcg_pixel_determine_rate()
636 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_pixel_set_rate()
640 src = ns_to_src(&rcg->s, ns); in clk_rcg_pixel_set_rate()
643 if (src == rcg->s.parent_map[i].cfg) { in clk_rcg_pixel_set_rate()
644 f.src = rcg->s.parent_map[i].src; in clk_rcg_pixel_set_rate()
653 for (; frac->num; frac++) { in clk_rcg_pixel_set_rate()
654 request = (rate * frac->den) / frac->num; in clk_rcg_pixel_set_rate()
656 if ((parent_rate < (request - delta)) || in clk_rcg_pixel_set_rate()
660 f.m = frac->num; in clk_rcg_pixel_set_rate()
661 f.n = frac->den; in clk_rcg_pixel_set_rate()
666 return -EINVAL; in clk_rcg_pixel_set_rate()
679 int pre_div_max = BIT(rcg->p.pre_div_width); in clk_rcg_esc_determine_rate()
683 if (req->rate == 0) in clk_rcg_esc_determine_rate()
684 return -EINVAL; in clk_rcg_esc_determine_rate()
686 src_rate = clk_hw_get_rate(req->best_parent_hw); in clk_rcg_esc_determine_rate()
688 div = src_rate / req->rate; in clk_rcg_esc_determine_rate()
691 req->best_parent_rate = src_rate; in clk_rcg_esc_determine_rate()
692 req->rate = src_rate / div; in clk_rcg_esc_determine_rate()
696 return -EINVAL; in clk_rcg_esc_determine_rate()
704 int pre_div_max = BIT(rcg->p.pre_div_width); in clk_rcg_esc_set_rate()
710 return -EINVAL; in clk_rcg_esc_set_rate()
712 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_esc_set_rate()
716 ns = ns_to_src(&rcg->s, ns); in clk_rcg_esc_set_rate()
719 if (ns == rcg->s.parent_map[i].cfg) { in clk_rcg_esc_set_rate()
720 f.src = rcg->s.parent_map[i].src; in clk_rcg_esc_set_rate()
732 return -EINVAL; in clk_rcg_esc_set_rate()
742 * This type of clock has a glitch-free mux that switches between the output of
760 f = qcom_find_freq(rcg->freq_tbl, rate); in clk_rcg_lcc_set_rate()
762 return -EINVAL; in clk_rcg_lcc_set_rate()
765 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); in clk_rcg_lcc_set_rate()
768 if (__clk_is_enabled(hw->clk)) in clk_rcg_lcc_set_rate()
769 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); in clk_rcg_lcc_set_rate()
780 return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); in clk_rcg_lcc_enable()
789 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); in clk_rcg_lcc_disable()
797 f = qcom_find_freq(rcg->freq_tbl, rate); in __clk_dyn_rcg_set_rate()
799 return -EINVAL; in __clk_dyn_rcg_set_rate()