Lines Matching +full:0 +full:x29000
66 { P_XO, 0 },
77 { P_XO, 0 },
89 { P_XO, 0 },
102 { P_XO, 0 },
115 { P_XO, 0 },
128 { P_XO, 0 },
139 { P_USB3PHY_0_PIPE, 0 },
149 { P_USB3PHY_1_PIPE, 0 },
159 { P_PCIE20_PHY0_PIPE, 0 },
169 { P_PCIE20_PHY1_PIPE, 0 },
181 { P_XO, 0 },
195 { P_XO, 0 },
209 { P_XO, 0 },
222 { P_XO, 0 },
237 { P_XO, 0 },
251 { P_XO, 0 },
265 { P_XO, 0 },
280 { P_XO, 0 },
294 { P_XO, 0 },
310 { P_XO, 0 },
329 { P_XO, 0 },
350 { P_XO, 0 },
368 { P_XO, 0 },
384 { P_XO, 0 },
400 { P_XO, 0 },
408 .offset = 0x21000,
411 .enable_reg = 0x0b000,
412 .enable_mask = BIT(0),
439 .offset = 0x21000,
453 .offset = 0x4a000,
456 .enable_reg = 0x0b000,
471 .offset = 0x4a000,
486 .offset = 0x24000,
489 .enable_reg = 0x0b000,
504 .offset = 0x24000,
519 .offset = 0x37000,
523 .enable_reg = 0x0b000,
538 .offset = 0x37000,
567 .offset = 0x25000,
571 .enable_reg = 0x0b000,
585 .offset = 0x25000,
600 .offset = 0x22000,
603 .enable_reg = 0x0b000,
617 .offset = 0x22000,
632 F(19200000, P_XO, 1, 0, 0),
633 F(50000000, P_GPLL0, 16, 0, 0),
634 F(100000000, P_GPLL0, 8, 0, 0),
639 .cmd_rcgr = 0x27000,
667 .halt_reg = 0x30000,
669 .enable_reg = 0x30000,
683 F(19200000, P_XO, 1, 0, 0),
684 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
685 F(50000000, P_GPLL0, 16, 0, 0),
690 .cmd_rcgr = 0x0200c,
704 F(4800000, P_XO, 4, 0, 0),
705 F(9600000, P_XO, 2, 0, 0),
708 F(19200000, P_XO, 1, 0, 0),
710 F(50000000, P_GPLL0, 16, 0, 0),
715 .cmd_rcgr = 0x02024,
729 .cmd_rcgr = 0x03000,
742 .cmd_rcgr = 0x03014,
756 .cmd_rcgr = 0x04000,
769 .cmd_rcgr = 0x04014,
783 .cmd_rcgr = 0x05000,
796 .cmd_rcgr = 0x05014,
810 .cmd_rcgr = 0x06000,
823 .cmd_rcgr = 0x06014,
837 .cmd_rcgr = 0x07000,
850 .cmd_rcgr = 0x07014,
868 F(19200000, P_XO, 1, 0, 0),
884 .cmd_rcgr = 0x02044,
898 .cmd_rcgr = 0x03034,
912 .cmd_rcgr = 0x04034,
926 .cmd_rcgr = 0x05034,
940 .cmd_rcgr = 0x06034,
954 .cmd_rcgr = 0x07034,
968 F(19200000, P_XO, 1, 0, 0),
969 F(200000000, P_GPLL0, 4, 0, 0),
974 .cmd_rcgr = 0x75054,
987 F(19200000, P_XO, 1, 0, 0),
991 .cmd_rcgr = 0x75024,
1005 .reg = 0x7501c,
1021 .cmd_rcgr = 0x76054,
1034 .cmd_rcgr = 0x76024,
1048 .reg = 0x7601c,
1068 F(96000000, P_GPLL2, 12, 0, 0),
1069 F(177777778, P_GPLL0, 4.5, 0, 0),
1070 F(192000000, P_GPLL2, 6, 0, 0),
1071 F(384000000, P_GPLL2, 3, 0, 0),
1076 .cmd_rcgr = 0x42004,
1090 F(19200000, P_XO, 1, 0, 0),
1091 F(160000000, P_GPLL0, 5, 0, 0),
1092 F(308570000, P_GPLL6, 3.5, 0, 0),
1096 .cmd_rcgr = 0x5d000,
1110 .cmd_rcgr = 0x43004,
1124 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1125 F(100000000, P_GPLL0, 8, 0, 0),
1126 F(133330000, P_GPLL0, 6, 0, 0),
1131 .cmd_rcgr = 0x3e00c,
1145 F(19200000, P_XO, 1, 0, 0),
1150 .cmd_rcgr = 0x3e05c,
1164 F(19200000, P_XO, 1, 0, 0),
1171 .cmd_rcgr = 0x3e020,
1185 .reg = 0x3e048,
1201 .cmd_rcgr = 0x3f00c,
1215 .cmd_rcgr = 0x3f05c,
1229 .cmd_rcgr = 0x3f020,
1243 .reg = 0x3f048,
1259 .halt_reg = 0x30018,
1261 .enable_reg = 0x30018,
1290 F(19200000, P_XO, 1, 0, 0),
1291 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1292 F(100000000, P_GPLL0, 8, 0, 0),
1293 F(133333333, P_GPLL0, 6, 0, 0),
1294 F(160000000, P_GPLL0, 5, 0, 0),
1295 F(200000000, P_GPLL0, 4, 0, 0),
1296 F(266666667, P_GPLL0, 3, 0, 0),
1301 .cmd_rcgr = 0x26004,
1329 F(19200000, P_XO, 1, 0, 0),
1330 F(200000000, P_GPLL0, 4, 0, 0),
1335 .cmd_rcgr = 0x68098,
1348 F(19200000, P_XO, 1, 0, 0),
1349 F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1354 .cmd_rcgr = 0x68088,
1381 F(19200000, P_XO, 1, 0, 0),
1382 F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1387 .cmd_rcgr = 0x68144,
1401 F(19200000, P_XO, 1, 0, 0),
1402 F(187200000, P_UBI32_PLL, 8, 0, 0),
1403 F(748800000, P_UBI32_PLL, 2, 0, 0),
1404 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1405 F(1689600000, P_UBI32_PLL, 1, 0, 0),
1410 .cmd_rcgr = 0x68104,
1424 .reg = 0x68118,
1425 .shift = 0,
1441 .cmd_rcgr = 0x68124,
1455 .reg = 0x68138,
1456 .shift = 0,
1472 F(19200000, P_XO, 1, 0, 0),
1473 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1478 .cmd_rcgr = 0x68090,
1491 F(19200000, P_XO, 1, 0, 0),
1492 F(400000000, P_GPLL0, 2, 0, 0),
1497 .cmd_rcgr = 0x68158,
1510 F(19200000, P_XO, 1, 0, 0),
1511 F(300000000, P_BIAS_PLL, 1, 0, 0),
1516 .cmd_rcgr = 0x68080,
1543 F(19200000, P_XO, 1, 0, 0),
1544 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1545 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1550 .cmd_rcgr = 0x68020,
1563 .reg = 0x68400,
1564 .shift = 0,
1580 F(19200000, P_XO, 1, 0, 0),
1581 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1582 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1587 .cmd_rcgr = 0x68028,
1600 .reg = 0x68404,
1601 .shift = 0,
1617 .cmd_rcgr = 0x68030,
1630 .reg = 0x68410,
1631 .shift = 0,
1647 .cmd_rcgr = 0x68038,
1660 .reg = 0x68414,
1661 .shift = 0,
1677 .cmd_rcgr = 0x68040,
1690 .reg = 0x68420,
1691 .shift = 0,
1707 .cmd_rcgr = 0x68048,
1720 .reg = 0x68424,
1721 .shift = 0,
1737 .cmd_rcgr = 0x68050,
1750 .reg = 0x68430,
1751 .shift = 0,
1767 .cmd_rcgr = 0x68058,
1780 .reg = 0x68434,
1781 .shift = 0,
1797 F(19200000, P_XO, 1, 0, 0),
1798 F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1799 F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1800 F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1801 F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1802 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1807 .cmd_rcgr = 0x68060,
1820 .reg = 0x68440,
1821 .shift = 0,
1837 F(19200000, P_XO, 1, 0, 0),
1838 F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1839 F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1840 F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1841 F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1842 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1847 .cmd_rcgr = 0x68068,
1860 .reg = 0x68444,
1861 .shift = 0,
1877 F(19200000, P_XO, 1, 0, 0),
1878 F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1879 F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1880 F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1881 F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1882 F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1887 .cmd_rcgr = 0x68070,
1900 .reg = 0x68450,
1901 .shift = 0,
1917 F(19200000, P_XO, 1, 0, 0),
1918 F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1919 F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1920 F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1921 F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1922 F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1927 .cmd_rcgr = 0x68078,
1940 .reg = 0x68454,
1941 .shift = 0,
1957 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1958 F(80000000, P_GPLL0, 10, 0, 0),
1959 F(100000000, P_GPLL0, 8, 0, 0),
1960 F(160000000, P_GPLL0, 5, 0, 0),
1965 .cmd_rcgr = 0x16004,
1978 F(19200000, P_XO, 1, 0, 0),
1983 .cmd_rcgr = 0x08004,
1997 .cmd_rcgr = 0x09004,
2011 .cmd_rcgr = 0x0a004,
2025 .halt_reg = 0x01008,
2027 .enable_reg = 0x01008,
2028 .enable_mask = BIT(0),
2042 .halt_reg = 0x02008,
2044 .enable_reg = 0x02008,
2045 .enable_mask = BIT(0),
2059 .halt_reg = 0x02004,
2061 .enable_reg = 0x02004,
2062 .enable_mask = BIT(0),
2076 .halt_reg = 0x03010,
2078 .enable_reg = 0x03010,
2079 .enable_mask = BIT(0),
2093 .halt_reg = 0x0300c,
2095 .enable_reg = 0x0300c,
2096 .enable_mask = BIT(0),
2110 .halt_reg = 0x04010,
2112 .enable_reg = 0x04010,
2113 .enable_mask = BIT(0),
2127 .halt_reg = 0x0400c,
2129 .enable_reg = 0x0400c,
2130 .enable_mask = BIT(0),
2144 .halt_reg = 0x05010,
2146 .enable_reg = 0x05010,
2147 .enable_mask = BIT(0),
2161 .halt_reg = 0x0500c,
2163 .enable_reg = 0x0500c,
2164 .enable_mask = BIT(0),
2178 .halt_reg = 0x06010,
2180 .enable_reg = 0x06010,
2181 .enable_mask = BIT(0),
2195 .halt_reg = 0x0600c,
2197 .enable_reg = 0x0600c,
2198 .enable_mask = BIT(0),
2212 .halt_reg = 0x07010,
2214 .enable_reg = 0x07010,
2215 .enable_mask = BIT(0),
2229 .halt_reg = 0x0700c,
2231 .enable_reg = 0x0700c,
2232 .enable_mask = BIT(0),
2246 .halt_reg = 0x0203c,
2248 .enable_reg = 0x0203c,
2249 .enable_mask = BIT(0),
2263 .halt_reg = 0x0302c,
2265 .enable_reg = 0x0302c,
2266 .enable_mask = BIT(0),
2280 .halt_reg = 0x0402c,
2282 .enable_reg = 0x0402c,
2283 .enable_mask = BIT(0),
2297 .halt_reg = 0x0502c,
2299 .enable_reg = 0x0502c,
2300 .enable_mask = BIT(0),
2314 .halt_reg = 0x0602c,
2316 .enable_reg = 0x0602c,
2317 .enable_mask = BIT(0),
2331 .halt_reg = 0x0702c,
2333 .enable_reg = 0x0702c,
2334 .enable_mask = BIT(0),
2348 .halt_reg = 0x13004,
2351 .enable_reg = 0x0b004,
2366 .halt_reg = 0x57024,
2368 .enable_reg = 0x57024,
2369 .enable_mask = BIT(0),
2383 .halt_reg = 0x57020,
2385 .enable_reg = 0x57020,
2386 .enable_mask = BIT(0),
2400 .halt_reg = 0x75010,
2402 .enable_reg = 0x75010,
2403 .enable_mask = BIT(0),
2417 .halt_reg = 0x75014,
2419 .enable_reg = 0x75014,
2420 .enable_mask = BIT(0),
2434 .halt_reg = 0x75008,
2436 .enable_reg = 0x75008,
2437 .enable_mask = BIT(0),
2451 .halt_reg = 0x7500c,
2453 .enable_reg = 0x7500c,
2454 .enable_mask = BIT(0),
2468 .halt_reg = 0x75018,
2471 .enable_reg = 0x75018,
2472 .enable_mask = BIT(0),
2486 .halt_reg = 0x26048,
2488 .enable_reg = 0x26048,
2489 .enable_mask = BIT(0),
2503 .halt_reg = 0x76010,
2505 .enable_reg = 0x76010,
2506 .enable_mask = BIT(0),
2520 .halt_reg = 0x76014,
2522 .enable_reg = 0x76014,
2523 .enable_mask = BIT(0),
2537 .halt_reg = 0x76008,
2539 .enable_reg = 0x76008,
2540 .enable_mask = BIT(0),
2554 .halt_reg = 0x7600c,
2556 .enable_reg = 0x7600c,
2557 .enable_mask = BIT(0),
2571 .halt_reg = 0x76018,
2574 .enable_reg = 0x76018,
2575 .enable_mask = BIT(0),
2589 .halt_reg = 0x2604c,
2591 .enable_reg = 0x2604c,
2592 .enable_mask = BIT(0),
2606 .halt_reg = 0x3e044,
2608 .enable_reg = 0x3e044,
2609 .enable_mask = BIT(0),
2623 .halt_reg = 0x26040,
2625 .enable_reg = 0x26040,
2626 .enable_mask = BIT(0),
2640 .halt_reg = 0x3e000,
2642 .enable_reg = 0x3e000,
2643 .enable_mask = BIT(0),
2657 .halt_reg = 0x3e008,
2659 .enable_reg = 0x3e008,
2660 .enable_mask = BIT(0),
2674 .halt_reg = 0x3e080,
2676 .enable_reg = 0x3e080,
2677 .enable_mask = BIT(0),
2691 .halt_reg = 0x3e040,
2694 .enable_reg = 0x3e040,
2695 .enable_mask = BIT(0),
2709 .halt_reg = 0x3e004,
2711 .enable_reg = 0x3e004,
2712 .enable_mask = BIT(0),
2726 .halt_reg = 0x3f044,
2728 .enable_reg = 0x3f044,
2729 .enable_mask = BIT(0),
2743 .halt_reg = 0x26044,
2745 .enable_reg = 0x26044,
2746 .enable_mask = BIT(0),
2760 .halt_reg = 0x3f000,
2762 .enable_reg = 0x3f000,
2763 .enable_mask = BIT(0),
2777 .halt_reg = 0x3f008,
2779 .enable_reg = 0x3f008,
2780 .enable_mask = BIT(0),
2794 .halt_reg = 0x3f080,
2796 .enable_reg = 0x3f080,
2797 .enable_mask = BIT(0),
2811 .halt_reg = 0x3f040,
2814 .enable_reg = 0x3f040,
2815 .enable_mask = BIT(0),
2829 .halt_reg = 0x3f004,
2831 .enable_reg = 0x3f004,
2832 .enable_mask = BIT(0),
2846 .halt_reg = 0x4201c,
2848 .enable_reg = 0x4201c,
2849 .enable_mask = BIT(0),
2863 .halt_reg = 0x42018,
2865 .enable_reg = 0x42018,
2866 .enable_mask = BIT(0),
2880 .halt_reg = 0x5d014,
2882 .enable_reg = 0x5d014,
2883 .enable_mask = BIT(0),
2897 .halt_reg = 0x4301c,
2899 .enable_reg = 0x4301c,
2900 .enable_mask = BIT(0),
2914 .halt_reg = 0x43018,
2916 .enable_reg = 0x43018,
2917 .enable_mask = BIT(0),
2931 .halt_reg = 0x1d03c,
2933 .enable_reg = 0x1d03c,
2934 .enable_mask = BIT(0),
2948 .halt_reg = 0x68174,
2950 .enable_reg = 0x68174,
2951 .enable_mask = BIT(0),
2965 .halt_reg = 0x68170,
2967 .enable_reg = 0x68170,
2968 .enable_mask = BIT(0),
2982 .halt_reg = 0x68160,
2984 .enable_reg = 0x68160,
2985 .enable_mask = BIT(0),
2999 .halt_reg = 0x68164,
3001 .enable_reg = 0x68164,
3002 .enable_mask = BIT(0),
3016 .halt_reg = 0x68318,
3018 .enable_reg = 0x68318,
3019 .enable_mask = BIT(0),
3033 .halt_reg = 0x6819c,
3035 .enable_reg = 0x6819c,
3036 .enable_mask = BIT(0),
3050 .halt_reg = 0x68198,
3052 .enable_reg = 0x68198,
3053 .enable_mask = BIT(0),
3067 .halt_reg = 0x68178,
3069 .enable_reg = 0x68178,
3070 .enable_mask = BIT(0),
3084 .halt_reg = 0x68168,
3086 .enable_reg = 0x68168,
3087 .enable_mask = BIT(0),
3101 .halt_reg = 0x6833c,
3103 .enable_reg = 0x6833c,
3104 .enable_mask = BIT(0),
3118 .halt_reg = 0x68194,
3120 .enable_reg = 0x68194,
3121 .enable_mask = BIT(0),
3135 .halt_reg = 0x68190,
3137 .enable_reg = 0x68190,
3138 .enable_mask = BIT(0),
3152 .halt_reg = 0x68338,
3154 .enable_reg = 0x68338,
3155 .enable_mask = BIT(0),
3169 .halt_reg = 0x6816c,
3171 .enable_reg = 0x6816c,
3172 .enable_mask = BIT(0),
3186 .halt_reg = 0x6830c,
3188 .enable_reg = 0x6830c,
3189 .enable_mask = BIT(0),
3203 .halt_reg = 0x68308,
3205 .enable_reg = 0x68308,
3206 .enable_mask = BIT(0),
3220 .halt_reg = 0x68314,
3222 .enable_reg = 0x68314,
3223 .enable_mask = BIT(0),
3237 .halt_reg = 0x68304,
3239 .enable_reg = 0x68304,
3240 .enable_mask = BIT(0),
3254 .halt_reg = 0x68300,
3256 .enable_reg = 0x68300,
3257 .enable_mask = BIT(0),
3271 .halt_reg = 0x68180,
3273 .enable_reg = 0x68180,
3274 .enable_mask = BIT(0),
3288 .halt_reg = 0x68188,
3290 .enable_reg = 0x68188,
3291 .enable_mask = BIT(0),
3305 .halt_reg = 0x68184,
3307 .enable_reg = 0x68184,
3308 .enable_mask = BIT(0),
3322 .halt_reg = 0x68270,
3324 .enable_reg = 0x68270,
3325 .enable_mask = BIT(0),
3339 .halt_reg = 0x68274,
3341 .enable_reg = 0x68274,
3342 .enable_mask = BIT(0),
3356 .halt_reg = 0x6820c,
3358 .enable_reg = 0x6820c,
3359 .enable_mask = BIT(0),
3373 .halt_reg = 0x68200,
3375 .enable_reg = 0x68200,
3376 .enable_mask = BIT(0),
3390 .halt_reg = 0x68204,
3392 .enable_reg = 0x68204,
3393 .enable_mask = BIT(0),
3407 .halt_reg = 0x68210,
3409 .enable_reg = 0x68210,
3410 .enable_mask = BIT(0),
3424 .halt_reg = 0x68208,
3426 .enable_reg = 0x68208,
3427 .enable_mask = BIT(0),
3441 .halt_reg = 0x6822c,
3443 .enable_reg = 0x6822c,
3444 .enable_mask = BIT(0),
3458 .halt_reg = 0x68220,
3460 .enable_reg = 0x68220,
3461 .enable_mask = BIT(0),
3475 .halt_reg = 0x68224,
3477 .enable_reg = 0x68224,
3478 .enable_mask = BIT(0),
3492 .halt_reg = 0x68230,
3494 .enable_reg = 0x68230,
3495 .enable_mask = BIT(0),
3509 .halt_reg = 0x68228,
3511 .enable_reg = 0x68228,
3512 .enable_mask = BIT(0),
3526 .halt_reg = 0x56308,
3528 .enable_reg = 0x56308,
3529 .enable_mask = BIT(0),
3543 .halt_reg = 0x5630c,
3545 .enable_reg = 0x5630c,
3546 .enable_mask = BIT(0),
3560 .halt_reg = 0x58004,
3562 .enable_reg = 0x58004,
3563 .enable_mask = BIT(0),
3577 .halt_reg = 0x56008,
3579 .enable_reg = 0x56008,
3580 .enable_mask = BIT(0),
3594 .halt_reg = 0x5600c,
3596 .enable_reg = 0x5600c,
3597 .enable_mask = BIT(0),
3611 .halt_reg = 0x56108,
3613 .enable_reg = 0x56108,
3614 .enable_mask = BIT(0),
3628 .halt_reg = 0x5610c,
3630 .enable_reg = 0x5610c,
3631 .enable_mask = BIT(0),
3645 .halt_reg = 0x56208,
3647 .enable_reg = 0x56208,
3648 .enable_mask = BIT(0),
3662 .halt_reg = 0x5620c,
3664 .enable_reg = 0x5620c,
3665 .enable_mask = BIT(0),
3679 .halt_reg = 0x68240,
3681 .enable_reg = 0x68240,
3682 .enable_mask = BIT(0),
3696 .halt_reg = 0x68244,
3698 .enable_reg = 0x68244,
3699 .enable_mask = BIT(0),
3713 .halt_reg = 0x68248,
3715 .enable_reg = 0x68248,
3716 .enable_mask = BIT(0),
3730 .halt_reg = 0x6824c,
3732 .enable_reg = 0x6824c,
3733 .enable_mask = BIT(0),
3747 .halt_reg = 0x68250,
3749 .enable_reg = 0x68250,
3750 .enable_mask = BIT(0),
3764 .halt_reg = 0x68254,
3766 .enable_reg = 0x68254,
3767 .enable_mask = BIT(0),
3781 .halt_reg = 0x68258,
3783 .enable_reg = 0x68258,
3784 .enable_mask = BIT(0),
3798 .halt_reg = 0x6825c,
3800 .enable_reg = 0x6825c,
3801 .enable_mask = BIT(0),
3815 .halt_reg = 0x68260,
3817 .enable_reg = 0x68260,
3818 .enable_mask = BIT(0),
3832 .halt_reg = 0x68264,
3834 .enable_reg = 0x68264,
3835 .enable_mask = BIT(0),
3849 .halt_reg = 0x68268,
3851 .enable_reg = 0x68268,
3852 .enable_mask = BIT(0),
3866 .halt_reg = 0x6826c,
3868 .enable_reg = 0x6826c,
3869 .enable_mask = BIT(0),
3883 .halt_reg = 0x68320,
3885 .enable_reg = 0x68320,
3886 .enable_mask = BIT(0),
3900 .halt_reg = 0x68324,
3902 .enable_reg = 0x68324,
3903 .enable_mask = BIT(0),
3917 .halt_reg = 0x68328,
3919 .enable_reg = 0x68328,
3920 .enable_mask = BIT(0),
3934 .halt_reg = 0x6832c,
3936 .enable_reg = 0x6832c,
3937 .enable_mask = BIT(0),
3951 .halt_reg = 0x68330,
3953 .enable_reg = 0x68330,
3954 .enable_mask = BIT(0),
3968 .halt_reg = 0x68334,
3970 .enable_reg = 0x68334,
3971 .enable_mask = BIT(0),
3985 .halt_reg = 0x56010,
3987 .enable_reg = 0x56010,
3988 .enable_mask = BIT(0),
4002 .halt_reg = 0x56014,
4004 .enable_reg = 0x56014,
4005 .enable_mask = BIT(0),
4019 .halt_reg = 0x56018,
4021 .enable_reg = 0x56018,
4022 .enable_mask = BIT(0),
4036 .halt_reg = 0x5601c,
4038 .enable_reg = 0x5601c,
4039 .enable_mask = BIT(0),
4053 .halt_reg = 0x56020,
4055 .enable_reg = 0x56020,
4056 .enable_mask = BIT(0),
4070 .halt_reg = 0x56024,
4072 .enable_reg = 0x56024,
4073 .enable_mask = BIT(0),
4087 .halt_reg = 0x56028,
4089 .enable_reg = 0x56028,
4090 .enable_mask = BIT(0),
4104 .halt_reg = 0x5602c,
4106 .enable_reg = 0x5602c,
4107 .enable_mask = BIT(0),
4121 .halt_reg = 0x56030,
4123 .enable_reg = 0x56030,
4124 .enable_mask = BIT(0),
4138 .halt_reg = 0x56034,
4140 .enable_reg = 0x56034,
4141 .enable_mask = BIT(0),
4155 .halt_reg = 0x56110,
4157 .enable_reg = 0x56110,
4158 .enable_mask = BIT(0),
4172 .halt_reg = 0x56114,
4174 .enable_reg = 0x56114,
4175 .enable_mask = BIT(0),
4189 .halt_reg = 0x56210,
4191 .enable_reg = 0x56210,
4192 .enable_mask = BIT(0),
4206 .halt_reg = 0x56214,
4208 .enable_reg = 0x56214,
4209 .enable_mask = BIT(0),
4223 .halt_reg = 0x16024,
4226 .enable_reg = 0x0b004,
4227 .enable_mask = BIT(0),
4241 .halt_reg = 0x16020,
4244 .enable_reg = 0x0b004,
4259 .halt_reg = 0x1601c,
4262 .enable_reg = 0x0b004,
4277 .halt_reg = 0x08000,
4279 .enable_reg = 0x08000,
4280 .enable_mask = BIT(0),
4294 .halt_reg = 0x09000,
4296 .enable_reg = 0x09000,
4297 .enable_mask = BIT(0),
4311 .halt_reg = 0x0a000,
4313 .enable_reg = 0x0a000,
4314 .enable_mask = BIT(0),
4565 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4566 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4567 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4568 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4569 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4570 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4571 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4572 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4573 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4574 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4575 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4576 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4577 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4578 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4579 [GCC_SMMU_BCR] = { 0x12000, 0 },
4580 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4581 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4582 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4583 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4584 [GCC_PRNG_BCR] = { 0x13000, 0 },
4585 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4586 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4587 [GCC_WCSS_BCR] = { 0x18000, 0 },
4588 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4589 [GCC_NSS_BCR] = { 0x19000, 0 },
4590 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4591 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4592 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4593 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4594 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4595 [GCC_TCSR_BCR] = { 0x28000, 0 },
4596 [GCC_QDSS_BCR] = { 0x29000, 0 },
4597 [GCC_DCD_BCR] = { 0x2a000, 0 },
4598 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4599 [GCC_MPM_BCR] = { 0x2c000, 0 },
4600 [GCC_SPMI_BCR] = { 0x2e000, 0 },
4601 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4602 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4603 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4604 [GCC_TLMM_BCR] = { 0x34000, 0 },
4605 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4606 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4607 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4608 [GCC_USB0_BCR] = { 0x3e070, 0 },
4609 [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4610 [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4611 [GCC_USB1_BCR] = { 0x3f070, 0 },
4612 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4613 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4614 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4615 [GCC_SDCC2_BCR] = { 0x43000, 0 },
4616 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4617 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4618 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4619 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4620 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4621 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4622 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4623 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4624 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4625 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4626 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4627 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4628 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4629 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4630 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4631 [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4632 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4633 [GCC_QPIC_BCR] = { 0x57018, 0 },
4634 [GCC_MDIO_BCR] = { 0x58000, 0 },
4635 [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4636 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4637 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4638 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4639 [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4640 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4641 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4642 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4643 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4644 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4645 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4646 [GCC_PCIE1_BCR] = { 0x76004, 0 },
4647 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4648 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4649 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4650 [GCC_DCC_BCR] = { 0x77000, 0 },
4651 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4652 [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4653 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4654 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4655 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4656 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4657 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4658 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4659 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4660 [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4661 [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4662 [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4663 [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4664 [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4665 [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4666 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4667 [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4668 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4669 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4670 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4671 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4672 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4673 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4674 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4675 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4676 [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4677 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4678 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4679 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4680 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4681 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4682 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4683 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4684 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4685 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4686 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4687 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4688 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4689 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4690 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4691 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4692 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4693 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4694 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4695 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4708 .max_register = 0x7fffc,
4724 for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) { in gcc_ipq8074_probe()