Lines Matching +full:0 +full:x29000
54 { P_XO, 0 },
64 { P_XO, 0 },
76 { P_XO, 0 },
90 { P_XO, 0 },
102 { P_XO, 0 },
112 { P_XO, 0 },
126 { P_XO, 0 },
138 { P_XO, 0, },
148 { P_XO, 0 },
160 { P_XO, 0 },
172 { P_XO, 0 },
184 { P_XO, 0 },
198 { P_XO, 0 },
212 { P_XO, 0 },
228 { P_XO, 0 },
244 { P_XO, 0 },
254 { P_XO, 0 },
268 .l_reg = 0x21004,
269 .m_reg = 0x21008,
270 .n_reg = 0x2100c,
271 .config_reg = 0x21010,
272 .mode_reg = 0x21000,
273 .status_reg = 0x2101c,
284 .enable_reg = 0x45000,
285 .enable_mask = BIT(0),
295 .l_reg = 0x20004,
296 .m_reg = 0x20008,
297 .n_reg = 0x2000c,
298 .config_reg = 0x20010,
299 .mode_reg = 0x20000,
300 .status_reg = 0x2001c,
311 .enable_reg = 0x45000,
322 .l_reg = 0x4a004,
323 .m_reg = 0x4a008,
324 .n_reg = 0x4a00c,
325 .config_reg = 0x4a010,
326 .mode_reg = 0x4a000,
327 .status_reg = 0x4a01c,
338 .enable_reg = 0x45000,
349 .l_reg = 0x23004,
350 .m_reg = 0x23008,
351 .n_reg = 0x2300c,
352 .config_reg = 0x23010,
353 .mode_reg = 0x23000,
354 .status_reg = 0x2301c,
365 .enable_reg = 0x45000,
376 .cmd_rcgr = 0x27000,
388 .cmd_rcgr = 0x26004,
401 F(80000000, P_GPLL0, 10, 0, 0),
406 .cmd_rcgr = 0x5a000,
420 F(19200000, P_XO, 1, 0, 0),
421 F(50000000, P_GPLL0, 16, 0, 0),
422 F(100000000, P_GPLL0, 8, 0, 0),
423 F(133330000, P_GPLL0, 6, 0, 0),
428 .cmd_rcgr = 0x46000,
441 F(100000000, P_GPLL0, 8, 0, 0),
442 F(200000000, P_GPLL0, 4, 0, 0),
447 .cmd_rcgr = 0x4e020,
460 .cmd_rcgr = 0x4f020,
473 F(19200000, P_XO, 1, 0, 0),
474 F(50000000, P_GPLL0_AUX, 16, 0, 0),
475 F(80000000, P_GPLL0_AUX, 10, 0, 0),
476 F(100000000, P_GPLL0_AUX, 8, 0, 0),
477 F(160000000, P_GPLL0_AUX, 5, 0, 0),
478 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
479 F(200000000, P_GPLL0_AUX, 4, 0, 0),
480 F(266670000, P_GPLL0_AUX, 3, 0, 0),
481 F(294912000, P_GPLL1, 3, 0, 0),
482 F(310000000, P_GPLL2, 3, 0, 0),
483 F(400000000, P_GPLL0_AUX, 2, 0, 0),
488 .cmd_rcgr = 0x59000,
501 F(50000000, P_GPLL0, 16, 0, 0),
502 F(80000000, P_GPLL0, 10, 0, 0),
503 F(100000000, P_GPLL0, 8, 0, 0),
504 F(160000000, P_GPLL0, 5, 0, 0),
505 F(177780000, P_GPLL0, 4.5, 0, 0),
506 F(200000000, P_GPLL0, 4, 0, 0),
507 F(266670000, P_GPLL0, 3, 0, 0),
508 F(320000000, P_GPLL0, 2.5, 0, 0),
509 F(400000000, P_GPLL0, 2, 0, 0),
510 F(465000000, P_GPLL2, 2, 0, 0),
515 .cmd_rcgr = 0x58000,
528 F(19200000, P_XO, 1, 0, 0),
529 F(50000000, P_GPLL0, 16, 0, 0),
534 .cmd_rcgr = 0x0200c,
548 F(4800000, P_XO, 4, 0, 0),
549 F(9600000, P_XO, 2, 0, 0),
551 F(19200000, P_XO, 1, 0, 0),
553 F(50000000, P_GPLL0, 16, 0, 0),
558 .cmd_rcgr = 0x02024,
572 .cmd_rcgr = 0x03000,
585 .cmd_rcgr = 0x03014,
599 .cmd_rcgr = 0x04000,
612 .cmd_rcgr = 0x04024,
626 .cmd_rcgr = 0x05000,
639 .cmd_rcgr = 0x05024,
653 .cmd_rcgr = 0x06000,
666 .cmd_rcgr = 0x06024,
680 .cmd_rcgr = 0x07000,
693 .cmd_rcgr = 0x07024,
711 F(19200000, P_XO, 1, 0, 0),
726 .cmd_rcgr = 0x02044,
740 .cmd_rcgr = 0x03034,
754 F(19200000, P_XO, 1, 0, 0),
759 .cmd_rcgr = 0x51000,
773 F(100000000, P_GPLL0, 8, 0, 0),
774 F(200000000, P_GPLL0, 4, 0, 0),
779 .cmd_rcgr = 0x54000,
793 .cmd_rcgr = 0x55000,
807 F(133330000, P_GPLL0, 6, 0, 0),
808 F(266670000, P_GPLL0, 3, 0, 0),
809 F(320000000, P_GPLL0, 2.5, 0, 0),
814 .cmd_rcgr = 0x57000,
827 F(9600000, P_XO, 2, 0, 0),
829 F(66670000, P_GPLL0, 12, 0, 0),
834 .cmd_rcgr = 0x52000,
848 .cmd_rcgr = 0x53000,
862 F(100000000, P_GPLL0, 8, 0, 0),
863 F(200000000, P_GPLL0, 4, 0, 0),
868 .cmd_rcgr = 0x4e000,
881 .cmd_rcgr = 0x4f000,
894 F(160000000, P_GPLL0, 5, 0, 0),
895 F(320000000, P_GPLL0, 2.5, 0, 0),
896 F(465000000, P_GPLL2, 2, 0, 0),
901 .cmd_rcgr = 0x58018,
914 F(50000000, P_GPLL0, 16, 0, 0),
915 F(80000000, P_GPLL0, 10, 0, 0),
916 F(100000000, P_GPLL0, 8, 0, 0),
917 F(160000000, P_GPLL0, 5, 0, 0),
922 .cmd_rcgr = 0x16004,
935 F(19200000, P_XO, 1, 0, 0),
940 .cmd_rcgr = 0x08004,
954 .cmd_rcgr = 0x09004,
968 .cmd_rcgr = 0x0a004,
982 .cmd_rcgr = 0x4d044,
995 F(19200000, P_XO, 1, 0, 0),
1000 .cmd_rcgr = 0x4d05c,
1013 F(50000000, P_GPLL0, 16, 0, 0),
1014 F(80000000, P_GPLL0, 10, 0, 0),
1015 F(100000000, P_GPLL0, 8, 0, 0),
1016 F(160000000, P_GPLL0, 5, 0, 0),
1017 F(177780000, P_GPLL0, 4.5, 0, 0),
1018 F(200000000, P_GPLL0, 4, 0, 0),
1019 F(266670000, P_GPLL0, 3, 0, 0),
1020 F(320000000, P_GPLL0, 2.5, 0, 0),
1025 .cmd_rcgr = 0x4d014,
1038 .cmd_rcgr = 0x4d000,
1052 F(19200000, P_XO, 1, 0, 0),
1057 .cmd_rcgr = 0x4d02c,
1070 F(64000000, P_GPLL0, 12.5, 0, 0),
1075 .cmd_rcgr = 0x44010,
1092 F(50000000, P_GPLL0, 16, 0, 0),
1093 F(100000000, P_GPLL0, 8, 0, 0),
1094 F(177770000, P_GPLL0, 4.5, 0, 0),
1099 .cmd_rcgr = 0x42004,
1117 F(50000000, P_GPLL0, 16, 0, 0),
1118 F(100000000, P_GPLL0, 8, 0, 0),
1119 F(200000000, P_GPLL0, 4, 0, 0),
1124 .cmd_rcgr = 0x43004,
1138 F(155000000, P_GPLL2, 6, 0, 0),
1139 F(310000000, P_GPLL2, 3, 0, 0),
1140 F(400000000, P_GPLL0, 2, 0, 0),
1145 .cmd_rcgr = 0x1207c,
1158 F(19200000, P_XO, 1, 0, 0),
1159 F(100000000, P_GPLL0, 8, 0, 0),
1160 F(200000000, P_GPLL0, 4, 0, 0),
1161 F(266500000, P_BIMC, 4, 0, 0),
1162 F(400000000, P_GPLL0, 2, 0, 0),
1163 F(533000000, P_BIMC, 2, 0, 0),
1168 .cmd_rcgr = 0x31028,
1182 F(80000000, P_GPLL0, 10, 0, 0),
1187 .cmd_rcgr = 0x41010,
1200 F(3200000, P_XO, 6, 0, 0),
1201 F(6400000, P_XO, 3, 0, 0),
1202 F(9600000, P_XO, 2, 0, 0),
1203 F(19200000, P_XO, 1, 0, 0),
1205 F(66670000, P_GPLL0, 12, 0, 0),
1206 F(80000000, P_GPLL0, 10, 0, 0),
1207 F(100000000, P_GPLL0, 8, 0, 0),
1212 .cmd_rcgr = 0x1c010,
1226 .halt_reg = 0x1c028,
1228 .enable_reg = 0x1c028,
1229 .enable_mask = BIT(0),
1243 .halt_reg = 0x1c024,
1245 .enable_reg = 0x1c024,
1246 .enable_mask = BIT(0),
1272 F(1600000, P_XO, 12, 0, 0),
1276 F(2400000, P_XO, 8, 0, 0),
1280 F(4800000, P_XO, 4, 0, 0),
1284 F(9600000, P_XO, 2, 0, 0),
1291 .cmd_rcgr = 0x1c054,
1305 .halt_reg = 0x1c068,
1307 .enable_reg = 0x1c068,
1308 .enable_mask = BIT(0),
1322 .cmd_rcgr = 0x1c06c,
1336 .halt_reg = 0x1c080,
1338 .enable_reg = 0x1c080,
1339 .enable_mask = BIT(0),
1353 .cmd_rcgr = 0x1c084,
1367 .halt_reg = 0x1c098,
1369 .enable_reg = 0x1c098,
1370 .enable_mask = BIT(0),
1384 F(19200000, P_XO, 1, 0, 0),
1389 .cmd_rcgr = 0x1c034,
1402 .halt_reg = 0x1c04c,
1404 .enable_reg = 0x1c04c,
1405 .enable_mask = BIT(0),
1419 .halt_reg = 0x1c050,
1421 .enable_reg = 0x1c050,
1422 .enable_mask = BIT(0),
1436 F(9600000, P_XO, 2, 0, 0),
1438 F(19200000, P_XO, 1, 0, 0),
1439 F(11289600, P_EXT_MCLK, 1, 0, 0),
1444 .cmd_rcgr = 0x1c09c,
1458 .halt_reg = 0x1c0b0,
1460 .enable_reg = 0x1c0b0,
1461 .enable_mask = BIT(0),
1475 .halt_reg = 0x1c000,
1477 .enable_reg = 0x1c000,
1478 .enable_mask = BIT(0),
1491 .halt_reg = 0x1c004,
1493 .enable_reg = 0x1c004,
1494 .enable_mask = BIT(0),
1507 F(100000000, P_GPLL0, 8, 0, 0),
1508 F(160000000, P_GPLL0, 5, 0, 0),
1509 F(228570000, P_GPLL0, 3.5, 0, 0),
1514 .cmd_rcgr = 0x4C000,
1528 .halt_reg = 0x01008,
1531 .enable_reg = 0x45004,
1545 .halt_reg = 0x01004,
1547 .enable_reg = 0x01004,
1548 .enable_mask = BIT(0),
1562 .halt_reg = 0x02008,
1564 .enable_reg = 0x02008,
1565 .enable_mask = BIT(0),
1579 .halt_reg = 0x02004,
1581 .enable_reg = 0x02004,
1582 .enable_mask = BIT(0),
1596 .halt_reg = 0x03010,
1598 .enable_reg = 0x03010,
1599 .enable_mask = BIT(0),
1613 .halt_reg = 0x0300c,
1615 .enable_reg = 0x0300c,
1616 .enable_mask = BIT(0),
1630 .halt_reg = 0x04020,
1632 .enable_reg = 0x04020,
1633 .enable_mask = BIT(0),
1647 .halt_reg = 0x0401c,
1649 .enable_reg = 0x0401c,
1650 .enable_mask = BIT(0),
1664 .halt_reg = 0x05020,
1666 .enable_reg = 0x05020,
1667 .enable_mask = BIT(0),
1681 .halt_reg = 0x0501c,
1683 .enable_reg = 0x0501c,
1684 .enable_mask = BIT(0),
1698 .halt_reg = 0x06020,
1700 .enable_reg = 0x06020,
1701 .enable_mask = BIT(0),
1715 .halt_reg = 0x0601c,
1717 .enable_reg = 0x0601c,
1718 .enable_mask = BIT(0),
1732 .halt_reg = 0x07020,
1734 .enable_reg = 0x07020,
1735 .enable_mask = BIT(0),
1749 .halt_reg = 0x0701c,
1751 .enable_reg = 0x0701c,
1752 .enable_mask = BIT(0),
1766 .halt_reg = 0x0203c,
1768 .enable_reg = 0x0203c,
1769 .enable_mask = BIT(0),
1783 .halt_reg = 0x0302c,
1785 .enable_reg = 0x0302c,
1786 .enable_mask = BIT(0),
1800 .halt_reg = 0x1300c,
1803 .enable_reg = 0x45004,
1817 .halt_reg = 0x5101c,
1819 .enable_reg = 0x5101c,
1820 .enable_mask = BIT(0),
1834 .halt_reg = 0x51018,
1836 .enable_reg = 0x51018,
1837 .enable_mask = BIT(0),
1851 .halt_reg = 0x4e040,
1853 .enable_reg = 0x4e040,
1854 .enable_mask = BIT(0),
1868 .halt_reg = 0x4e03c,
1870 .enable_reg = 0x4e03c,
1871 .enable_mask = BIT(0),
1885 .halt_reg = 0x4e048,
1887 .enable_reg = 0x4e048,
1888 .enable_mask = BIT(0),
1902 .halt_reg = 0x4e058,
1904 .enable_reg = 0x4e058,
1905 .enable_mask = BIT(0),
1919 .halt_reg = 0x4e050,
1921 .enable_reg = 0x4e050,
1922 .enable_mask = BIT(0),
1936 .halt_reg = 0x4f040,
1938 .enable_reg = 0x4f040,
1939 .enable_mask = BIT(0),
1953 .halt_reg = 0x4f03c,
1955 .enable_reg = 0x4f03c,
1956 .enable_mask = BIT(0),
1970 .halt_reg = 0x4f048,
1972 .enable_reg = 0x4f048,
1973 .enable_mask = BIT(0),
1987 .halt_reg = 0x4f058,
1989 .enable_reg = 0x4f058,
1990 .enable_mask = BIT(0),
2004 .halt_reg = 0x4f050,
2006 .enable_reg = 0x4f050,
2007 .enable_mask = BIT(0),
2021 .halt_reg = 0x58050,
2023 .enable_reg = 0x58050,
2024 .enable_mask = BIT(0),
2038 .halt_reg = 0x54018,
2040 .enable_reg = 0x54018,
2041 .enable_mask = BIT(0),
2055 .halt_reg = 0x55018,
2057 .enable_reg = 0x55018,
2058 .enable_mask = BIT(0),
2072 .halt_reg = 0x50004,
2074 .enable_reg = 0x50004,
2075 .enable_mask = BIT(0),
2089 .halt_reg = 0x57020,
2091 .enable_reg = 0x57020,
2092 .enable_mask = BIT(0),
2106 .halt_reg = 0x57024,
2108 .enable_reg = 0x57024,
2109 .enable_mask = BIT(0),
2123 .halt_reg = 0x57028,
2125 .enable_reg = 0x57028,
2126 .enable_mask = BIT(0),
2140 .halt_reg = 0x52018,
2142 .enable_reg = 0x52018,
2143 .enable_mask = BIT(0),
2157 .halt_reg = 0x53018,
2159 .enable_reg = 0x53018,
2160 .enable_mask = BIT(0),
2174 .halt_reg = 0x5600c,
2176 .enable_reg = 0x5600c,
2177 .enable_mask = BIT(0),
2191 .halt_reg = 0x4e01c,
2193 .enable_reg = 0x4e01c,
2194 .enable_mask = BIT(0),
2208 .halt_reg = 0x4f01c,
2210 .enable_reg = 0x4f01c,
2211 .enable_mask = BIT(0),
2225 .halt_reg = 0x5a014,
2227 .enable_reg = 0x5a014,
2228 .enable_mask = BIT(0),
2242 .halt_reg = 0x56004,
2244 .enable_reg = 0x56004,
2245 .enable_mask = BIT(0),
2259 .halt_reg = 0x58040,
2261 .enable_reg = 0x58040,
2262 .enable_mask = BIT(0),
2276 .halt_reg = 0x5803c,
2278 .enable_reg = 0x5803c,
2279 .enable_mask = BIT(0),
2293 .halt_reg = 0x58038,
2295 .enable_reg = 0x58038,
2296 .enable_mask = BIT(0),
2310 .halt_reg = 0x58044,
2312 .enable_reg = 0x58044,
2313 .enable_mask = BIT(0),
2327 .halt_reg = 0x58048,
2329 .enable_reg = 0x58048,
2330 .enable_mask = BIT(0),
2344 .halt_reg = 0x16024,
2347 .enable_reg = 0x45004,
2348 .enable_mask = BIT(0),
2362 .halt_reg = 0x16020,
2365 .enable_reg = 0x45004,
2380 .halt_reg = 0x1601c,
2383 .enable_reg = 0x45004,
2398 .halt_reg = 0x59024,
2400 .enable_reg = 0x59024,
2401 .enable_mask = BIT(0),
2415 .halt_reg = 0x08000,
2417 .enable_reg = 0x08000,
2418 .enable_mask = BIT(0),
2432 .halt_reg = 0x09000,
2434 .enable_reg = 0x09000,
2435 .enable_mask = BIT(0),
2449 .halt_reg = 0x0a000,
2451 .enable_reg = 0x0a000,
2452 .enable_mask = BIT(0),
2466 .halt_reg = 0x4d07c,
2468 .enable_reg = 0x4d07c,
2469 .enable_mask = BIT(0),
2483 .halt_reg = 0x4d080,
2485 .enable_reg = 0x4d080,
2486 .enable_mask = BIT(0),
2500 .halt_reg = 0x4d094,
2502 .enable_reg = 0x4d094,
2503 .enable_mask = BIT(0),
2517 .halt_reg = 0x4d098,
2519 .enable_reg = 0x4d098,
2520 .enable_mask = BIT(0),
2534 .halt_reg = 0x4D088,
2536 .enable_reg = 0x4D088,
2537 .enable_mask = BIT(0),
2551 .halt_reg = 0x4d084,
2553 .enable_reg = 0x4d084,
2554 .enable_mask = BIT(0),
2568 .halt_reg = 0x4d090,
2570 .enable_reg = 0x4d090,
2571 .enable_mask = BIT(0),
2585 .halt_reg = 0x49000,
2587 .enable_reg = 0x49000,
2588 .enable_mask = BIT(0),
2602 .halt_reg = 0x49004,
2604 .enable_reg = 0x49004,
2605 .enable_mask = BIT(0),
2619 .halt_reg = 0x59028,
2621 .enable_reg = 0x59028,
2622 .enable_mask = BIT(0),
2636 .halt_reg = 0x59020,
2638 .enable_reg = 0x59020,
2639 .enable_mask = BIT(0),
2653 .halt_reg = 0x4400c,
2655 .enable_reg = 0x4400c,
2656 .enable_mask = BIT(0),
2670 .halt_reg = 0x44004,
2672 .enable_reg = 0x44004,
2673 .enable_mask = BIT(0),
2687 .halt_reg = 0x13004,
2690 .enable_reg = 0x45004,
2704 .halt_reg = 0x4201c,
2706 .enable_reg = 0x4201c,
2707 .enable_mask = BIT(0),
2721 .halt_reg = 0x42018,
2723 .enable_reg = 0x42018,
2724 .enable_mask = BIT(0),
2738 .halt_reg = 0x4301c,
2740 .enable_reg = 0x4301c,
2741 .enable_mask = BIT(0),
2755 .halt_reg = 0x43018,
2757 .enable_reg = 0x43018,
2758 .enable_mask = BIT(0),
2772 .cmd_rcgr = 0x32004,
2785 .halt_reg = 0x12018,
2787 .enable_reg = 0x4500c,
2801 .halt_reg = 0x12020,
2803 .enable_reg = 0x4500c,
2817 .halt_reg = 0x12044,
2819 .enable_reg = 0x4500c,
2834 .halt_reg = 0x31024,
2836 .enable_reg = 0x31024,
2837 .enable_mask = BIT(0),
2851 .halt_reg = 0x31040,
2853 .enable_reg = 0x31040,
2854 .enable_mask = BIT(0),
2868 .halt_reg = 0x12034,
2870 .enable_reg = 0x4500c,
2885 .halt_reg = 0x1201c,
2887 .enable_reg = 0x4500c,
2902 .halt_reg = 0x12038,
2904 .enable_reg = 0x4500c,
2919 .halt_reg = 0x12014,
2921 .enable_reg = 0x4500c,
2936 .halt_reg = 0x1203c,
2938 .enable_reg = 0x4500c,
2953 .halt_reg = 0x4102c,
2955 .enable_reg = 0x4102c,
2956 .enable_mask = BIT(0),
2970 .halt_reg = 0x41008,
2972 .enable_reg = 0x41008,
2973 .enable_mask = BIT(0),
2987 .halt_reg = 0x41004,
2989 .enable_reg = 0x41004,
2990 .enable_mask = BIT(0),
3004 .halt_reg = 0x4c020,
3006 .enable_reg = 0x4c020,
3007 .enable_mask = BIT(0),
3021 .halt_reg = 0x4c024,
3023 .enable_reg = 0x4c024,
3024 .enable_mask = BIT(0),
3038 .halt_reg = 0x4c01c,
3040 .enable_reg = 0x4c01c,
3041 .enable_mask = BIT(0),
3055 .gdscr = 0x4c018,
3063 .gdscr = 0x4d078,
3071 .gdscr = 0x5701c,
3079 .gdscr = 0x58034,
3087 .gdscr = 0x5901c,
3267 [GCC_BLSP1_BCR] = { 0x01000 },
3268 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3269 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3270 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3271 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3272 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3273 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3274 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3275 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3276 [GCC_IMEM_BCR] = { 0x0e000 },
3277 [GCC_SMMU_BCR] = { 0x12000 },
3278 [GCC_APSS_TCU_BCR] = { 0x12050 },
3279 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3280 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3281 [GCC_PRNG_BCR] = { 0x13000 },
3282 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3283 [GCC_CRYPTO_BCR] = { 0x16000 },
3284 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3285 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3286 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3287 [GCC_DEHR_BCR] = { 0x1f000 },
3288 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3289 [GCC_PCNOC_BCR] = { 0x27018 },
3290 [GCC_TCSR_BCR] = { 0x28000 },
3291 [GCC_QDSS_BCR] = { 0x29000 },
3292 [GCC_DCD_BCR] = { 0x2a000 },
3293 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3294 [GCC_MPM_BCR] = { 0x2c000 },
3295 [GCC_SPMI_BCR] = { 0x2e000 },
3296 [GCC_SPDM_BCR] = { 0x2f000 },
3297 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3298 [GCC_BIMC_BCR] = { 0x31000 },
3299 [GCC_RBCPR_BCR] = { 0x33000 },
3300 [GCC_TLMM_BCR] = { 0x34000 },
3301 [GCC_USB_HS_BCR] = { 0x41000 },
3302 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3303 [GCC_SDCC1_BCR] = { 0x42000 },
3304 [GCC_SDCC2_BCR] = { 0x43000 },
3305 [GCC_PDM_BCR] = { 0x44000 },
3306 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3307 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3308 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3309 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3310 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3311 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3312 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3313 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3314 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3315 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3316 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3317 [GCC_MMSS_BCR] = { 0x4b000 },
3318 [GCC_VENUS0_BCR] = { 0x4c014 },
3319 [GCC_MDSS_BCR] = { 0x4d074 },
3320 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3321 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3322 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3323 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3324 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3325 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3326 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3327 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3328 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3329 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3330 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3331 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3332 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3333 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3334 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3335 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3336 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3337 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3338 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3339 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3340 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3341 [GCC_OXILI_BCR] = { 0x59018 },
3342 [GCC_GMEM_BCR] = { 0x5902c },
3343 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3344 [GCC_MDP_TBU_BCR] = { 0x62000 },
3345 [GCC_GFX_TBU_BCR] = { 0x63000 },
3346 [GCC_GFX_TCU_BCR] = { 0x64000 },
3347 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3348 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3349 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3350 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3351 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3352 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3353 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3354 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3355 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3356 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3363 .max_register = 0x80000,