Lines Matching +full:0 +full:x29000
58 { P_XO, 0 },
68 { P_XO, 0 },
78 { P_XO, 0 },
90 { P_XO, 0 },
102 { P_XO, 0 },
114 { P_XO, 0 },
128 { P_XO, 0 },
142 { P_XO, 0 },
160 { P_XO, 0 },
191 .offset = 0x00000,
194 .enable_reg = 0x52000,
195 .enable_mask = BIT(0),
217 .offset = 0x00000,
228 .offset = 0x77000,
231 .enable_reg = 0x52000,
243 .offset = 0x77000,
254 F(19200000, P_XO, 1, 0, 0),
255 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
256 F(100000000, P_GPLL0, 6, 0, 0),
257 F(150000000, P_GPLL0, 4, 0, 0),
258 F(200000000, P_GPLL0, 3, 0, 0),
259 F(240000000, P_GPLL0, 2.5, 0, 0),
264 .cmd_rcgr = 0x0401c,
277 F(19200000, P_XO, 1, 0, 0),
278 F(37500000, P_GPLL0, 16, 0, 0),
279 F(75000000, P_GPLL0, 8, 0, 0),
284 .cmd_rcgr = 0x0500c,
297 F(19200000, P_XO, 1, 0, 0),
298 F(37500000, P_GPLL0, 16, 0, 0),
299 F(50000000, P_GPLL0, 12, 0, 0),
300 F(75000000, P_GPLL0, 8, 0, 0),
301 F(100000000, P_GPLL0, 6, 0, 0),
306 .cmd_rcgr = 0x06014,
319 F(19200000, P_XO, 1, 0, 0),
320 F(120000000, P_GPLL0, 5, 0, 0),
321 F(150000000, P_GPLL0, 4, 0, 0),
326 .cmd_rcgr = 0x0f014,
340 F(19200000, P_XO, 1, 0, 0),
345 .cmd_rcgr = 0x0f028,
358 F(1200000, P_XO, 16, 0, 0),
363 .cmd_rcgr = 0x5000c,
376 F(120000000, P_GPLL0, 5, 0, 0),
381 .cmd_rcgr = 0x12010,
395 .cmd_rcgr = 0x12024,
412 F(50000000, P_GPLL0, 12, 0, 0),
413 F(96000000, P_GPLL4, 4, 0, 0),
414 F(192000000, P_GPLL4, 2, 0, 0),
415 F(384000000, P_GPLL4, 1, 0, 0),
420 .cmd_rcgr = 0x13010,
434 F(19200000, P_XO, 1, 0, 0),
435 F(150000000, P_GPLL0, 4, 0, 0),
436 F(300000000, P_GPLL0, 2, 0, 0),
441 .cmd_rcgr = 0x13024,
458 F(50000000, P_GPLL0, 12, 0, 0),
459 F(100000000, P_GPLL0, 6, 0, 0),
460 F(200000000, P_GPLL0, 3, 0, 0),
465 .cmd_rcgr = 0x14010,
479 .cmd_rcgr = 0x15010,
497 F(50000000, P_GPLL0, 12, 0, 0),
498 F(100000000, P_GPLL0, 6, 0, 0),
503 .cmd_rcgr = 0x16010,
518 F(4800000, P_XO, 4, 0, 0),
519 F(9600000, P_XO, 2, 0, 0),
521 F(19200000, P_XO, 1, 0, 0),
523 F(50000000, P_GPLL0, 12, 0, 0),
528 .cmd_rcgr = 0x1900c,
542 F(19200000, P_XO, 1, 0, 0),
543 F(50000000, P_GPLL0, 12, 0, 0),
548 .cmd_rcgr = 0x19020,
565 F(19200000, P_XO, 1, 0, 0),
568 F(40000000, P_GPLL0, 15, 0, 0),
570 F(48000000, P_GPLL0, 12.5, 0, 0),
574 F(60000000, P_GPLL0, 10, 0, 0),
575 F(63157895, P_GPLL0, 9.5, 0, 0),
580 .cmd_rcgr = 0x1a00c,
594 .cmd_rcgr = 0x1b00c,
608 .cmd_rcgr = 0x1b020,
621 .cmd_rcgr = 0x1c00c,
635 .cmd_rcgr = 0x1d00c,
649 .cmd_rcgr = 0x1d020,
662 .cmd_rcgr = 0x1e00c,
676 .cmd_rcgr = 0x1f00c,
690 .cmd_rcgr = 0x1f020,
703 .cmd_rcgr = 0x2000c,
717 .cmd_rcgr = 0x2100c,
731 .cmd_rcgr = 0x21020,
744 .cmd_rcgr = 0x2200c,
758 .cmd_rcgr = 0x2300c,
772 .cmd_rcgr = 0x23020,
785 .cmd_rcgr = 0x2400c,
799 .cmd_rcgr = 0x2600c,
813 .cmd_rcgr = 0x26020,
826 .cmd_rcgr = 0x2700c,
840 .cmd_rcgr = 0x2800c,
854 .cmd_rcgr = 0x28020,
867 .cmd_rcgr = 0x2900c,
881 .cmd_rcgr = 0x2a00c,
895 .cmd_rcgr = 0x2a020,
908 .cmd_rcgr = 0x2b00c,
922 .cmd_rcgr = 0x2c00c,
936 .cmd_rcgr = 0x2c020,
949 .cmd_rcgr = 0x2d00c,
963 .cmd_rcgr = 0x2e00c,
977 .cmd_rcgr = 0x2e020,
990 .cmd_rcgr = 0x2f00c,
1004 .cmd_rcgr = 0x3000c,
1018 .cmd_rcgr = 0x30020,
1031 .cmd_rcgr = 0x3100c,
1045 F(60000000, P_GPLL0, 10, 0, 0),
1050 .cmd_rcgr = 0x33010,
1068 .cmd_rcgr = 0x36010,
1082 .cmd_rcgr = 0x43014,
1094 .cmd_rcgr = 0x48040,
1107 .cmd_rcgr = 0x48058,
1119 F(19200000, P_XO, 1, 0, 0),
1120 F(100000000, P_GPLL0, 6, 0, 0),
1121 F(200000000, P_GPLL0, 3, 0, 0),
1126 .cmd_rcgr = 0x64004,
1140 .cmd_rcgr = 0x65004,
1154 .cmd_rcgr = 0x66004,
1173 .cmd_rcgr = 0x6c000,
1187 F(100000000, P_GPLL0, 6, 0, 0),
1188 F(200000000, P_GPLL0, 3, 0, 0),
1189 F(240000000, P_GPLL0, 2.5, 0, 0),
1194 .cmd_rcgr = 0x75024,
1208 F(19200000, P_XO, 1, 0, 0),
1209 F(150000000, P_GPLL0, 4, 0, 0),
1210 F(300000000, P_GPLL0, 2, 0, 0),
1215 .cmd_rcgr = 0x76014,
1228 F(75000000, P_GPLL0, 8, 0, 0),
1229 F(150000000, P_GPLL0, 4, 0, 0),
1230 F(256000000, P_GPLL4, 1.5, 0, 0),
1231 F(300000000, P_GPLL0, 2, 0, 0),
1236 .cmd_rcgr = 0x8b00c,
1249 .halt_reg = 0x0f03c,
1251 .enable_reg = 0x0f03c,
1252 .enable_mask = BIT(0),
1264 .halt_reg = 0x75038,
1266 .enable_reg = 0x75038,
1267 .enable_mask = BIT(0),
1279 .halt_reg = 0x6010,
1281 .enable_reg = 0x6010,
1282 .enable_mask = BIT(0),
1294 .halt_reg = 0x9008,
1296 .enable_reg = 0x9008,
1297 .enable_mask = BIT(0),
1309 .halt_reg = 0x9010,
1311 .enable_reg = 0x9010,
1312 .enable_mask = BIT(0),
1322 .halt_reg = 0x0f008,
1324 .enable_reg = 0x0f008,
1325 .enable_mask = BIT(0),
1337 .halt_reg = 0x0f00c,
1339 .enable_reg = 0x0f00c,
1340 .enable_mask = BIT(0),
1352 .halt_reg = 0x0f010,
1354 .enable_reg = 0x0f010,
1355 .enable_mask = BIT(0),
1367 .halt_reg = 0x50000,
1369 .enable_reg = 0x50000,
1370 .enable_mask = BIT(0),
1382 .halt_reg = 0x50004,
1385 .enable_reg = 0x50004,
1386 .enable_mask = BIT(0),
1398 .halt_reg = 0x12004,
1400 .enable_reg = 0x12004,
1401 .enable_mask = BIT(0),
1413 .halt_reg = 0x12008,
1415 .enable_reg = 0x12008,
1416 .enable_mask = BIT(0),
1428 .halt_reg = 0x1200c,
1430 .enable_reg = 0x1200c,
1431 .enable_mask = BIT(0),
1443 .halt_reg = 0x6a004,
1445 .enable_reg = 0x6a004,
1446 .enable_mask = BIT(0),
1458 .halt_reg = 0x13004,
1460 .enable_reg = 0x13004,
1461 .enable_mask = BIT(0),
1473 .halt_reg = 0x13008,
1475 .enable_reg = 0x13008,
1476 .enable_mask = BIT(0),
1488 .halt_reg = 0x13038,
1490 .enable_reg = 0x13038,
1491 .enable_mask = BIT(0),
1503 .halt_reg = 0x14004,
1505 .enable_reg = 0x14004,
1506 .enable_mask = BIT(0),
1518 .halt_reg = 0x14008,
1520 .enable_reg = 0x14008,
1521 .enable_mask = BIT(0),
1533 .halt_reg = 0x15004,
1535 .enable_reg = 0x15004,
1536 .enable_mask = BIT(0),
1548 .halt_reg = 0x15008,
1550 .enable_reg = 0x15008,
1551 .enable_mask = BIT(0),
1563 .halt_reg = 0x16004,
1565 .enable_reg = 0x16004,
1566 .enable_mask = BIT(0),
1578 .halt_reg = 0x16008,
1580 .enable_reg = 0x16008,
1581 .enable_mask = BIT(0),
1593 .halt_reg = 0x17004,
1596 .enable_reg = 0x52004,
1609 .halt_reg = 0x17008,
1612 .enable_reg = 0x52004,
1625 .halt_reg = 0x19004,
1627 .enable_reg = 0x19004,
1628 .enable_mask = BIT(0),
1640 .halt_reg = 0x19008,
1642 .enable_reg = 0x19008,
1643 .enable_mask = BIT(0),
1655 .halt_reg = 0x1a004,
1657 .enable_reg = 0x1a004,
1658 .enable_mask = BIT(0),
1670 .halt_reg = 0x1b004,
1672 .enable_reg = 0x1b004,
1673 .enable_mask = BIT(0),
1685 .halt_reg = 0x1b008,
1687 .enable_reg = 0x1b008,
1688 .enable_mask = BIT(0),
1700 .halt_reg = 0x1c004,
1702 .enable_reg = 0x1c004,
1703 .enable_mask = BIT(0),
1715 .halt_reg = 0x1d004,
1717 .enable_reg = 0x1d004,
1718 .enable_mask = BIT(0),
1730 .halt_reg = 0x1d008,
1732 .enable_reg = 0x1d008,
1733 .enable_mask = BIT(0),
1745 .halt_reg = 0x1e004,
1747 .enable_reg = 0x1e004,
1748 .enable_mask = BIT(0),
1760 .halt_reg = 0x1f004,
1762 .enable_reg = 0x1f004,
1763 .enable_mask = BIT(0),
1775 .halt_reg = 0x1f008,
1777 .enable_reg = 0x1f008,
1778 .enable_mask = BIT(0),
1790 .halt_reg = 0x20004,
1792 .enable_reg = 0x20004,
1793 .enable_mask = BIT(0),
1805 .halt_reg = 0x21004,
1807 .enable_reg = 0x21004,
1808 .enable_mask = BIT(0),
1820 .halt_reg = 0x21008,
1822 .enable_reg = 0x21008,
1823 .enable_mask = BIT(0),
1835 .halt_reg = 0x22004,
1837 .enable_reg = 0x22004,
1838 .enable_mask = BIT(0),
1850 .halt_reg = 0x23004,
1852 .enable_reg = 0x23004,
1853 .enable_mask = BIT(0),
1865 .halt_reg = 0x23008,
1867 .enable_reg = 0x23008,
1868 .enable_mask = BIT(0),
1880 .halt_reg = 0x24004,
1882 .enable_reg = 0x24004,
1883 .enable_mask = BIT(0),
1895 .halt_reg = 0x25004,
1898 .enable_reg = 0x52004,
1911 .halt_reg = 0x25008,
1914 .enable_reg = 0x52004,
1927 .halt_reg = 0x26004,
1929 .enable_reg = 0x26004,
1930 .enable_mask = BIT(0),
1942 .halt_reg = 0x26008,
1944 .enable_reg = 0x26008,
1945 .enable_mask = BIT(0),
1957 .halt_reg = 0x27004,
1959 .enable_reg = 0x27004,
1960 .enable_mask = BIT(0),
1972 .halt_reg = 0x28004,
1974 .enable_reg = 0x28004,
1975 .enable_mask = BIT(0),
1987 .halt_reg = 0x28008,
1989 .enable_reg = 0x28008,
1990 .enable_mask = BIT(0),
2002 .halt_reg = 0x29004,
2004 .enable_reg = 0x29004,
2005 .enable_mask = BIT(0),
2017 .halt_reg = 0x2a004,
2019 .enable_reg = 0x2a004,
2020 .enable_mask = BIT(0),
2032 .halt_reg = 0x2a008,
2034 .enable_reg = 0x2a008,
2035 .enable_mask = BIT(0),
2047 .halt_reg = 0x2b004,
2049 .enable_reg = 0x2b004,
2050 .enable_mask = BIT(0),
2062 .halt_reg = 0x2c004,
2064 .enable_reg = 0x2c004,
2065 .enable_mask = BIT(0),
2077 .halt_reg = 0x2c008,
2079 .enable_reg = 0x2c008,
2080 .enable_mask = BIT(0),
2092 .halt_reg = 0x2d004,
2094 .enable_reg = 0x2d004,
2095 .enable_mask = BIT(0),
2107 .halt_reg = 0x2e004,
2109 .enable_reg = 0x2e004,
2110 .enable_mask = BIT(0),
2122 .halt_reg = 0x2e008,
2124 .enable_reg = 0x2e008,
2125 .enable_mask = BIT(0),
2137 .halt_reg = 0x2f004,
2139 .enable_reg = 0x2f004,
2140 .enable_mask = BIT(0),
2152 .halt_reg = 0x30004,
2154 .enable_reg = 0x30004,
2155 .enable_mask = BIT(0),
2167 .halt_reg = 0x30008,
2169 .enable_reg = 0x30008,
2170 .enable_mask = BIT(0),
2182 .halt_reg = 0x31004,
2184 .enable_reg = 0x31004,
2185 .enable_mask = BIT(0),
2197 .halt_reg = 0x33004,
2199 .enable_reg = 0x33004,
2200 .enable_mask = BIT(0),
2212 .halt_reg = 0x3300c,
2214 .enable_reg = 0x3300c,
2215 .enable_mask = BIT(0),
2227 .halt_reg = 0x34004,
2230 .enable_reg = 0x52004,
2243 .halt_reg = 0x36004,
2245 .enable_reg = 0x36004,
2246 .enable_mask = BIT(0),
2258 .halt_reg = 0x36008,
2260 .enable_reg = 0x36008,
2261 .enable_mask = BIT(0),
2273 .halt_reg = 0x3600c,
2275 .enable_reg = 0x3600c,
2276 .enable_mask = BIT(0),
2288 .halt_reg = 0x38004,
2291 .enable_reg = 0x52004,
2304 .halt_reg = 0x46018,
2306 .enable_reg = 0x46018,
2307 .enable_mask = BIT(0),
2317 .halt_reg = 0x4800c,
2319 .enable_reg = 0x4800c,
2320 .enable_mask = BIT(0),
2332 .halt_reg = 0x64000,
2334 .enable_reg = 0x64000,
2335 .enable_mask = BIT(0),
2347 .halt_reg = 0x65000,
2349 .enable_reg = 0x65000,
2350 .enable_mask = BIT(0),
2362 .halt_reg = 0x66000,
2364 .enable_reg = 0x66000,
2365 .enable_mask = BIT(0),
2377 .halt_reg = 0x6b008,
2379 .enable_reg = 0x6b008,
2380 .enable_mask = BIT(0),
2392 .halt_reg = 0x6b00c,
2394 .enable_reg = 0x6b00c,
2395 .enable_mask = BIT(0),
2407 .halt_reg = 0x6b010,
2409 .enable_reg = 0x6b010,
2410 .enable_mask = BIT(0),
2422 .halt_reg = 0x6b014,
2424 .enable_reg = 0x6b014,
2425 .enable_mask = BIT(0),
2437 .halt_reg = 0x6b018,
2440 .enable_reg = 0x6b018,
2441 .enable_mask = BIT(0),
2453 .halt_reg = 0x6d008,
2455 .enable_reg = 0x6d008,
2456 .enable_mask = BIT(0),
2468 .halt_reg = 0x6d00c,
2470 .enable_reg = 0x6d00c,
2471 .enable_mask = BIT(0),
2483 .halt_reg = 0x6d010,
2485 .enable_reg = 0x6d010,
2486 .enable_mask = BIT(0),
2498 .halt_reg = 0x6d014,
2500 .enable_reg = 0x6d014,
2501 .enable_mask = BIT(0),
2513 .halt_reg = 0x6d018,
2516 .enable_reg = 0x6d018,
2517 .enable_mask = BIT(0),
2529 .halt_reg = 0x6e008,
2531 .enable_reg = 0x6e008,
2532 .enable_mask = BIT(0),
2544 .halt_reg = 0x6e00c,
2546 .enable_reg = 0x6e00c,
2547 .enable_mask = BIT(0),
2559 .halt_reg = 0x6e010,
2561 .enable_reg = 0x6e010,
2562 .enable_mask = BIT(0),
2574 .halt_reg = 0x6e014,
2576 .enable_reg = 0x6e014,
2577 .enable_mask = BIT(0),
2589 .halt_reg = 0x6e018,
2592 .enable_reg = 0x6e018,
2593 .enable_mask = BIT(0),
2605 .halt_reg = 0x6f004,
2607 .enable_reg = 0x6f004,
2608 .enable_mask = BIT(0),
2620 .halt_reg = 0x6f008,
2622 .enable_reg = 0x6f008,
2623 .enable_mask = BIT(0),
2635 .halt_reg = 0x75008,
2637 .enable_reg = 0x75008,
2638 .enable_mask = BIT(0),
2650 .halt_reg = 0x7500c,
2652 .enable_reg = 0x7500c,
2653 .enable_mask = BIT(0),
2677 .halt_reg = 0x75010,
2679 .enable_reg = 0x75010,
2680 .enable_mask = BIT(0),
2704 .halt_reg = 0x7d010,
2707 .enable_reg = 0x7d010,
2708 .enable_mask = BIT(0),
2717 .halt_reg = 0x7d014,
2720 .enable_reg = 0x7d014,
2721 .enable_mask = BIT(0),
2730 .halt_reg = 0x75014,
2732 .enable_reg = 0x75014,
2733 .enable_mask = BIT(0),
2745 .halt_reg = 0x75018,
2748 .enable_reg = 0x75018,
2749 .enable_mask = BIT(0),
2761 .halt_reg = 0x7501c,
2764 .enable_reg = 0x7501c,
2765 .enable_mask = BIT(0),
2777 .halt_reg = 0x75020,
2780 .enable_reg = 0x75020,
2781 .enable_mask = BIT(0),
2805 .halt_reg = 0x7600c,
2807 .enable_reg = 0x7600c,
2808 .enable_mask = BIT(0),
2820 .halt_reg = 0x76010,
2822 .enable_reg = 0x76010,
2823 .enable_mask = BIT(0),
2837 .enable_reg = 0x76030,
2838 .enable_mask = BIT(0),
2849 .enable_reg = 0x76034,
2850 .enable_mask = BIT(0),
2859 .halt_reg = 0x81008,
2861 .enable_reg = 0x81008,
2862 .enable_mask = BIT(0),
2874 .halt_reg = 0x8100c,
2876 .enable_reg = 0x8100c,
2877 .enable_mask = BIT(0),
2889 .halt_reg = 0x81014,
2891 .enable_reg = 0x81014,
2892 .enable_mask = BIT(0),
2904 .halt_reg = 0x81018,
2906 .enable_reg = 0x81018,
2907 .enable_mask = BIT(0),
2919 .halt_reg = 0x83014,
2921 .enable_reg = 0x83014,
2922 .enable_mask = BIT(0),
2934 .halt_reg = 0x83018,
2936 .enable_reg = 0x83018,
2937 .enable_mask = BIT(0),
2949 .halt_reg = 0x8b004,
2951 .enable_reg = 0x8b004,
2952 .enable_mask = BIT(0),
2964 .halt_reg = 0x8b008,
2966 .enable_reg = 0x8b008,
2967 .enable_mask = BIT(0),
2979 .halt_reg = 0x8800C,
2981 .enable_reg = 0x8800C,
2982 .enable_mask = BIT(0),
2993 .halt_reg = 0x88000,
2995 .enable_reg = 0x88000,
2996 .enable_mask = BIT(0),
3007 .halt_reg = 0x88008,
3009 .enable_reg = 0x88008,
3010 .enable_mask = BIT(0),
3021 .halt_reg = 0x88010,
3023 .enable_reg = 0x88010,
3024 .enable_mask = BIT(0),
3035 .halt_reg = 0x88014,
3037 .enable_reg = 0x88014,
3038 .enable_mask = BIT(0),
3049 .halt_reg = 0x88018,
3051 .enable_reg = 0x88018,
3052 .enable_mask = BIT(0),
3071 .gdscr = 0x81004,
3072 .gds_hw_ctrl = 0x81028,
3081 .gdscr = 0x7d024,
3090 .gdscr = 0x7d034,
3099 .gdscr = 0x7d038,
3108 .gdscr = 0xf004,
3116 .gdscr = 0x6b004,
3124 .gdscr = 0x6d004,
3132 .gdscr = 0x6e004,
3140 .gdscr = 0x75004,
3347 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3348 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3349 [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3350 [GCC_IMEM_BCR] = { 0x8000 },
3351 [GCC_MMSS_BCR] = { 0x9000 },
3352 [GCC_PIMEM_BCR] = { 0x0a000 },
3353 [GCC_QDSS_BCR] = { 0x0c000 },
3354 [GCC_USB_30_BCR] = { 0x0f000 },
3355 [GCC_USB_20_BCR] = { 0x12000 },
3356 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3357 [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3358 [GCC_USB3_PHY_BCR] = { 0x50020 },
3359 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3360 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3361 [GCC_SDCC1_BCR] = { 0x13000 },
3362 [GCC_SDCC2_BCR] = { 0x14000 },
3363 [GCC_SDCC3_BCR] = { 0x15000 },
3364 [GCC_SDCC4_BCR] = { 0x16000 },
3365 [GCC_BLSP1_BCR] = { 0x17000 },
3366 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3367 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3368 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3369 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3370 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3371 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3372 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3373 [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3374 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3375 [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3376 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3377 [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3378 [GCC_BLSP2_BCR] = { 0x25000 },
3379 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3380 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3381 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3382 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3383 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3384 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3385 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3386 [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3387 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3388 [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3389 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3390 [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3391 [GCC_PDM_BCR] = { 0x33000 },
3392 [GCC_PRNG_BCR] = { 0x34000 },
3393 [GCC_TSIF_BCR] = { 0x36000 },
3394 [GCC_TCSR_BCR] = { 0x37000 },
3395 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3396 [GCC_MSG_RAM_BCR] = { 0x39000 },
3397 [GCC_TLMM_BCR] = { 0x3a000 },
3398 [GCC_MPM_BCR] = { 0x3b000 },
3399 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3400 [GCC_SPMI_BCR] = { 0x3f000 },
3401 [GCC_SPDM_BCR] = { 0x40000 },
3402 [GCC_CE1_BCR] = { 0x41000 },
3403 [GCC_BIMC_BCR] = { 0x44000 },
3404 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3405 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3406 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3407 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3408 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3409 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3410 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3411 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3412 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3413 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3414 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3415 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3416 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3417 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3418 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3419 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3420 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3421 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3422 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3423 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3424 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3425 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3426 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3427 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3428 [GCC_PCIE_0_BCR] = { 0x6b000 },
3429 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3430 [GCC_PCIE_1_BCR] = { 0x6d000 },
3431 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3432 [GCC_PCIE_2_BCR] = { 0x6e000 },
3433 [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3434 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3435 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3436 [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3437 [GCC_DCD_BCR] = { 0x70000 },
3438 [GCC_OBT_ODT_BCR] = { 0x73000 },
3439 [GCC_UFS_BCR] = { 0x75000 },
3440 [GCC_SSC_BCR] = { 0x63000 },
3441 [GCC_VS_BCR] = { 0x7a000 },
3442 [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3443 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3444 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3445 [GCC_DCC_BCR] = { 0x84000 },
3446 [GCC_IPA_BCR] = { 0x89000 },
3447 [GCC_QSPI_BCR] = { 0x8b000 },
3448 [GCC_SKL_BCR] = { 0x8c000 },
3449 [GCC_MSMPU_BCR] = { 0x8d000 },
3450 [GCC_MSS_Q6_BCR] = { 0x8e000 },
3451 [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3452 [GCC_MSS_RESTART] = { 0x8f008 },
3459 .max_register = 0x8f010,
3493 regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); in gcc_msm8996_probe()
3495 for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) { in gcc_msm8996_probe()