Lines Matching +full:clock +full:- +full:name
2 * r8a7790 Common Clock Framework support
13 #include <linux/clk-provider.h>
23 #include "clk-div6.h"
30 * struct div6_clock - CPG 6 bit divider clock
31 * @hw: handle between common and hardware-specific interfaces
32 * @reg: IO-remapped register
33 * @div: divisor value (1-64)
34 * @src_shift: Shift to access the register bits to select the parent clock
35 * @src_width: Number of register bits to select the parent clock (may be 0)
37 * @nb: Notifier block to save/restore clock state for system resume
53 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_enable() local
56 val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
57 | CPG_DIV6_DIV(clock->div - 1); in cpg_div6_clock_enable()
58 writel(val, clock->reg); in cpg_div6_clock_enable()
65 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_disable() local
68 val = readl(clock->reg); in cpg_div6_clock_disable()
71 * DIV6 clocks require the divisor field to be non-zero when stopping in cpg_div6_clock_disable()
72 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be in cpg_div6_clock_disable()
73 * re-enabled later if the divisor field is changed when stopping the in cpg_div6_clock_disable()
74 * clock in cpg_div6_clock_disable()
78 writel(val, clock->reg); in cpg_div6_clock_disable()
83 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_is_enabled() local
85 return !(readl(clock->reg) & CPG_DIV6_CKSTP); in cpg_div6_clock_is_enabled()
91 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_recalc_rate() local
93 return parent_rate / clock->div; in cpg_div6_clock_recalc_rate()
119 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_set_rate() local
123 clock->div = div; in cpg_div6_clock_set_rate()
125 val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK; in cpg_div6_clock_set_rate()
126 /* Only program the new divisor if the clock isn't stopped. */ in cpg_div6_clock_set_rate()
128 writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); in cpg_div6_clock_set_rate()
135 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_get_parent() local
139 if (clock->src_width == 0) in cpg_div6_clock_get_parent()
142 hw_index = (readl(clock->reg) >> clock->src_shift) & in cpg_div6_clock_get_parent()
143 (BIT(clock->src_width) - 1); in cpg_div6_clock_get_parent()
145 if (clock->parents[i] == hw_index) in cpg_div6_clock_get_parent()
149 pr_err("%s: %s DIV6 clock set to invalid parent %u\n", in cpg_div6_clock_get_parent()
156 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_set_parent() local
161 return -EINVAL; in cpg_div6_clock_set_parent()
163 mask = ~((BIT(clock->src_width) - 1) << clock->src_shift); in cpg_div6_clock_set_parent()
164 hw_index = clock->parents[index]; in cpg_div6_clock_set_parent()
166 writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift), in cpg_div6_clock_set_parent()
167 clock->reg); in cpg_div6_clock_set_parent()
186 struct div6_clock *clock = container_of(nb, struct div6_clock, nb); in cpg_div6_clock_notifier_call() local
194 * R/SH-Mobile SoCs, while the resume functionality is only in cpg_div6_clock_notifier_call()
195 * needed on R-Car Gen3. in cpg_div6_clock_notifier_call()
197 if (__clk_get_enable_count(clock->hw.clk)) in cpg_div6_clock_notifier_call()
198 cpg_div6_clock_enable(&clock->hw); in cpg_div6_clock_notifier_call()
200 cpg_div6_clock_disable(&clock->hw); in cpg_div6_clock_notifier_call()
208 * cpg_div6_register - Register a DIV6 clock
209 * @name: Name of the DIV6 clock
210 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
212 * @reg: Mapped register used to control the DIV6 clock
215 struct clk * __init cpg_div6_register(const char *name, in cpg_div6_register() argument
223 struct div6_clock *clock; in cpg_div6_register() local
227 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in cpg_div6_register()
228 if (!clock) in cpg_div6_register()
229 return ERR_PTR(-ENOMEM); in cpg_div6_register()
231 clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents), in cpg_div6_register()
233 if (!clock->parents) { in cpg_div6_register()
234 clk = ERR_PTR(-ENOMEM); in cpg_div6_register()
238 clock->reg = reg; in cpg_div6_register()
241 * Read the divisor. Disabling the clock overwrites the divisor, so we in cpg_div6_register()
244 clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; in cpg_div6_register()
248 /* fixed parent clock */ in cpg_div6_register()
249 clock->src_shift = clock->src_width = 0; in cpg_div6_register()
252 /* clock with EXSRC bits 6-7 */ in cpg_div6_register()
253 clock->src_shift = 6; in cpg_div6_register()
254 clock->src_width = 2; in cpg_div6_register()
257 /* VCLK with EXSRC bits 12-14 */ in cpg_div6_register()
258 clock->src_shift = 12; in cpg_div6_register()
259 clock->src_width = 3; in cpg_div6_register()
262 pr_err("%s: invalid number of parents for DIV6 clock %s\n", in cpg_div6_register()
263 __func__, name); in cpg_div6_register()
264 clk = ERR_PTR(-EINVAL); in cpg_div6_register()
272 clock->parents[valid_parents] = i; in cpg_div6_register()
277 /* Register the clock. */ in cpg_div6_register()
278 init.name = name; in cpg_div6_register()
284 clock->hw.init = &init; in cpg_div6_register()
286 clk = clk_register(NULL, &clock->hw); in cpg_div6_register()
291 clock->nb.notifier_call = cpg_div6_clock_notifier_call; in cpg_div6_register()
292 raw_notifier_chain_register(notifiers, &clock->nb); in cpg_div6_register()
298 kfree(clock->parents); in cpg_div6_register()
300 kfree(clock); in cpg_div6_register()
308 const char *clk_name = np->name; in cpg_div6_clock_init()
315 pr_err("%s: no parent found for %s DIV6 clock\n", in cpg_div6_clock_init()
316 __func__, np->name); in cpg_div6_clock_init()
327 pr_err("%s: failed to map %s DIV6 clock register\n", in cpg_div6_clock_init()
328 __func__, np->name); in cpg_div6_clock_init()
333 of_property_read_string(np, "clock-output-names", &clk_name); in cpg_div6_clock_init()
340 pr_err("%s: failed to register %s DIV6 clock (%ld)\n", in cpg_div6_clock_init()
341 __func__, np->name, PTR_ERR(clk)); in cpg_div6_clock_init()
355 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);