Lines Matching +full:clock +full:- +full:mult
13 #include <linux/clk-provider.h>
22 #include <linux/soc/renesas/rcar-rst.h>
40 /* -----------------------------------------------------------------------------
41 * Z Clock
43 * Traits of this clock:
44 * prepare - clk_prepare only ensures that parents are prepared
45 * enable - clk_enable only ensures that parents are enabled
46 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
47 * parent - fixed parent. No clk_set_parent support
62 unsigned int mult; in cpg_z_clk_recalc_rate() local
65 val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; in cpg_z_clk_recalc_rate()
66 mult = 32 - val; in cpg_z_clk_recalc_rate()
68 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
75 unsigned int mult; in cpg_z_clk_round_rate() local
80 mult = div_u64((u64)rate * 32, prate); in cpg_z_clk_round_rate()
81 mult = clamp(mult, 1U, 32U); in cpg_z_clk_round_rate()
83 return *parent_rate / 32 * mult; in cpg_z_clk_round_rate()
90 unsigned int mult; in cpg_z_clk_set_rate() local
94 mult = div_u64((u64)rate * 32, parent_rate); in cpg_z_clk_set_rate()
95 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
97 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) in cpg_z_clk_set_rate()
98 return -EBUSY; in cpg_z_clk_set_rate()
100 val = readl(zclk->reg); in cpg_z_clk_set_rate()
102 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; in cpg_z_clk_set_rate()
103 writel(val, zclk->reg); in cpg_z_clk_set_rate()
107 * clock change completion. in cpg_z_clk_set_rate()
109 kick = readl(zclk->kick_reg); in cpg_z_clk_set_rate()
111 writel(kick, zclk->kick_reg); in cpg_z_clk_set_rate()
122 for (i = 1000; i; i--) { in cpg_z_clk_set_rate()
123 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) in cpg_z_clk_set_rate()
129 return -ETIMEDOUT; in cpg_z_clk_set_rate()
147 return ERR_PTR(-ENOMEM); in cpg_z_clk_register()
155 zclk->reg = cpg->reg + CPG_FRQCRC; in cpg_z_clk_register()
156 zclk->kick_reg = cpg->reg + CPG_FRQCRB; in cpg_z_clk_register()
157 zclk->hw.init = &init; in cpg_z_clk_register()
159 clk = clk_register(NULL, &zclk->hw); in cpg_z_clk_register()
176 return ERR_PTR(-ENOMEM); in cpg_rcan_clk_register()
178 fixed->mult = 1; in cpg_rcan_clk_register()
179 fixed->div = 6; in cpg_rcan_clk_register()
184 return ERR_PTR(-ENOMEM); in cpg_rcan_clk_register()
187 gate->reg = cpg->reg + CPG_RCANCKCR; in cpg_rcan_clk_register()
188 gate->bit_idx = 8; in cpg_rcan_clk_register()
189 gate->flags = CLK_GATE_SET_TO_DISABLE; in cpg_rcan_clk_register()
190 gate->lock = &cpg->lock; in cpg_rcan_clk_register()
193 &fixed->hw, &clk_fixed_factor_ops, in cpg_rcan_clk_register()
194 &gate->hw, &clk_gate_ops, 0); in cpg_rcan_clk_register()
219 return ERR_PTR(-ENOMEM); in cpg_adsp_clk_register()
221 div->reg = cpg->reg + CPG_ADSPCKCR; in cpg_adsp_clk_register()
222 div->width = 4; in cpg_adsp_clk_register()
223 div->table = cpg_adsp_div_table; in cpg_adsp_clk_register()
224 div->lock = &cpg->lock; in cpg_adsp_clk_register()
229 return ERR_PTR(-ENOMEM); in cpg_adsp_clk_register()
232 gate->reg = cpg->reg + CPG_ADSPCKCR; in cpg_adsp_clk_register()
233 gate->bit_idx = 8; in cpg_adsp_clk_register()
234 gate->flags = CLK_GATE_SET_TO_DISABLE; in cpg_adsp_clk_register()
235 gate->lock = &cpg->lock; in cpg_adsp_clk_register()
238 &div->hw, &clk_divider_ops, in cpg_adsp_clk_register()
239 &gate->hw, &clk_gate_ops, 0); in cpg_adsp_clk_register()
248 /* -----------------------------------------------------------------------------
249 * CPG Clock Data
255 *---------------------------------------------------
274 unsigned int pll0_mult; /* For R-Car V2H and E2 only */
297 /* -----------------------------------------------------------------------------
304 "renesas,r8a7792-cpg-clocks",
305 "renesas,r8a7794-cpg-clocks",
317 unsigned int mult = 1; in rcar_gen2_cpg_register_clock() local
322 div = config->extal_div; in rcar_gen2_cpg_register_clock()
324 /* PLL0 is a configurable multiplier clock. Register it as a in rcar_gen2_cpg_register_clock()
325 * fixed factor clock for now as there's no generic multiplier in rcar_gen2_cpg_register_clock()
326 * clock implementation and we currently have no need to change in rcar_gen2_cpg_register_clock()
330 /* R-Car V2H and E2 do not have PLL0CR */ in rcar_gen2_cpg_register_clock()
331 mult = config->pll0_mult; in rcar_gen2_cpg_register_clock()
334 u32 value = readl(cpg->reg + CPG_PLL0CR); in rcar_gen2_cpg_register_clock()
335 mult = ((value >> 24) & ((1 << 7) - 1)) + 1; in rcar_gen2_cpg_register_clock()
340 mult = config->pll1_mult / 2; in rcar_gen2_cpg_register_clock()
343 mult = config->pll3_mult; in rcar_gen2_cpg_register_clock()
370 return ERR_PTR(-EINVAL); in rcar_gen2_cpg_register_clock()
375 mult, div); in rcar_gen2_cpg_register_clock()
378 cpg->reg + CPG_SDCKCR, shift, in rcar_gen2_cpg_register_clock()
379 4, 0, table, &cpg->lock); in rcar_gen2_cpg_register_clock()
408 /* Backward-compatibility with old DT */ in rcar_gen2_cpg_clocks_init()
413 num_clks = of_property_count_strings(np, "clock-output-names"); in rcar_gen2_cpg_clocks_init()
428 spin_lock_init(&cpg->lock); in rcar_gen2_cpg_clocks_init()
430 cpg->data.clks = clks; in rcar_gen2_cpg_clocks_init()
431 cpg->data.clk_num = num_clks; in rcar_gen2_cpg_clocks_init()
433 cpg->reg = of_iomap(np, 0); in rcar_gen2_cpg_clocks_init()
434 if (WARN_ON(cpg->reg == NULL)) in rcar_gen2_cpg_clocks_init()
443 of_property_read_string_index(np, "clock-output-names", i, in rcar_gen2_cpg_clocks_init()
448 pr_err("%s: failed to register %s %s clock (%ld)\n", in rcar_gen2_cpg_clocks_init()
449 __func__, np->name, name, PTR_ERR(clk)); in rcar_gen2_cpg_clocks_init()
451 cpg->data.clks[i] = clk; in rcar_gen2_cpg_clocks_init()
454 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); in rcar_gen2_cpg_clocks_init()
458 CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",