Lines Matching full:mult
71 * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
93 unsigned int mult; in cpg_z_clk_recalc_rate() local
97 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate()
100 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2); in cpg_z_clk_recalc_rate()
108 unsigned int mult; in cpg_z_clk_round_rate() local
110 mult = div_u64(rate * 32ULL, prate); in cpg_z_clk_round_rate()
111 mult = clamp(mult, 1U, 32U); in cpg_z_clk_round_rate()
113 return (u64)prate * mult / 32; in cpg_z_clk_round_rate()
120 unsigned int mult; in cpg_z_clk_set_rate() local
125 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); in cpg_z_clk_set_rate()
126 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
132 val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask; in cpg_z_clk_set_rate()
435 unsigned int mult = 1; in rcar_gen3_cpg_clk_register() local
456 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_gen3_cpg_clk_register()
458 mult *= 2; in rcar_gen3_cpg_clk_register()
462 mult = cpg_pll_config->pll1_mult; in rcar_gen3_cpg_clk_register()
474 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_gen3_cpg_clk_register()
476 mult *= 2; in rcar_gen3_cpg_clk_register()
480 mult = cpg_pll_config->pll3_mult; in rcar_gen3_cpg_clk_register()
492 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_gen3_cpg_clk_register()
494 mult *= 2; in rcar_gen3_cpg_clk_register()
547 mult = 1; in rcar_gen3_cpg_clk_register()
563 __clk_get_name(parent), 0, mult, div); in rcar_gen3_cpg_clk_register()