17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
21 #include "clk.h"
50  * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
58 	unsigned long rate = clk_get_rate(hw->clk);  in rockchip_mmc_get_phase()
65 		return -EINVAL;  in rockchip_mmc_get_phase()
67 	raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);  in rockchip_mmc_get_phase()
87 	unsigned long rate = clk_get_rate(hw->clk);  in rockchip_mmc_set_phase()
95 	 * MMC host to the card, which expects the phase clock inherits  in rockchip_mmc_set_phase()
106 		pr_err("%s: invalid clk rate\n", __func__);  in rockchip_mmc_set_phase()
107 		return -EINVAL;  in rockchip_mmc_set_phase()
115 	 * actually go non-monotonic.  We don't go _too_ monotonic  in rockchip_mmc_set_phase()
134 	 * don't overflow 32-bit / 64-bit numbers.  in rockchip_mmc_set_phase()
147 	writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),  in rockchip_mmc_set_phase()
148 	       mmc_clock->reg);  in rockchip_mmc_set_phase()
150 	pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",  in rockchip_mmc_set_phase()
152 		mmc_clock->reg, raw_value>>(mmc_clock->shift),  in rockchip_mmc_set_phase()
175 	 * the intput data, which expects the fixed phase after the tuning  in rockchip_mmc_clk_rate_notify()
176 	 * process. However if the clock rate is changed, the phase is stale  in rockchip_mmc_clk_rate_notify()
177 	 * and may break the data sampling. So here we try to restore the phase  in rockchip_mmc_clk_rate_notify()
182 	 * since we only set the default sample phase and drive phase later on.  in rockchip_mmc_clk_rate_notify()
184 	 * set the max-frequency to match the boards' ability but we can't go  in rockchip_mmc_clk_rate_notify()
187 	if (ndata->old_rate <= ndata->new_rate)  in rockchip_mmc_clk_rate_notify()
191 		mmc_clock->cached_phase =  in rockchip_mmc_clk_rate_notify()
192 			rockchip_mmc_get_phase(&mmc_clock->hw);  in rockchip_mmc_clk_rate_notify()
193 	else if (mmc_clock->cached_phase != -EINVAL &&  in rockchip_mmc_clk_rate_notify()
195 		rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);  in rockchip_mmc_clk_rate_notify()
200 struct clk *rockchip_clk_register_mmc(const char *name,  in rockchip_clk_register_mmc()
206 	struct clk *clk;  in rockchip_clk_register_mmc()  local
211 		return ERR_PTR(-ENOMEM);  in rockchip_clk_register_mmc()
219 	mmc_clock->hw.init = &init;  in rockchip_clk_register_mmc()
220 	mmc_clock->reg = reg;  in rockchip_clk_register_mmc()
221 	mmc_clock->shift = shift;  in rockchip_clk_register_mmc()
223 	clk = clk_register(NULL, &mmc_clock->hw);  in rockchip_clk_register_mmc()
224 	if (IS_ERR(clk)) {  in rockchip_clk_register_mmc()
225 		ret = PTR_ERR(clk);  in rockchip_clk_register_mmc()
229 	mmc_clock->clk_rate_change_nb.notifier_call =  in rockchip_clk_register_mmc()
231 	ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);  in rockchip_clk_register_mmc()
235 	return clk;  in rockchip_clk_register_mmc()
237 	clk_unregister(clk);  in rockchip_clk_register_mmc()