16  * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
17  * clock for CPU domain. The rates of these auxiliary clocks are related to the
22  * clock and the corresponding rate changes of the auxillary clocks of the CPU
25  * registers to acheive a fast co-oridinated rate change for all the CPU domain
26  * clocks.
30  * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
38 #include <linux/clk-provider.h>
39 #include "clk-cpu.h"
103 	pr_err("%s: re-parenting mux timed-out\n", __func__);  in wait_until_mux_stable()
106 /* common round rate callback useable for all types of CPU clocks */
115 /* common recalc rate callback useable for all types of CPU clocks */
150 /* handler for pre-rate change notification from parent clock */
154 	const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;  in exynos_cpuclk_pre_rate_change()
155 	unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);  in exynos_cpuclk_pre_rate_change()
161 	while ((cfg_data->prate * 1000) != ndata->new_rate) {  in exynos_cpuclk_pre_rate_change()
162 		if (cfg_data->prate == 0)  in exynos_cpuclk_pre_rate_change()
163 			return -EINVAL;  in exynos_cpuclk_pre_rate_change()
167 	spin_lock_irqsave(cpuclk->lock, flags);  in exynos_cpuclk_pre_rate_change()
170 	 * For the selected PLL clock frequency, get the pre-defined divider  in exynos_cpuclk_pre_rate_change()
174 	div0 = cfg_data->div0;  in exynos_cpuclk_pre_rate_change()
175 	if (cpuclk->flags & CLK_CPU_HAS_DIV1) {  in exynos_cpuclk_pre_rate_change()
176 		div1 = cfg_data->div1;  in exynos_cpuclk_pre_rate_change()
188 	 * (this can result in too high speed of armclk output clocks).  in exynos_cpuclk_pre_rate_change()
190 	if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {  in exynos_cpuclk_pre_rate_change()
191 		unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);  in exynos_cpuclk_pre_rate_change()
193 		alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;  in exynos_cpuclk_pre_rate_change()
196 		if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {  in exynos_cpuclk_pre_rate_change()
217 	if (cpuclk->flags & CLK_CPU_HAS_DIV1) {  in exynos_cpuclk_pre_rate_change()
223 	spin_unlock_irqrestore(cpuclk->lock, flags);  in exynos_cpuclk_pre_rate_change()
227 /* handler for post-rate change notification from parent clock */
231 	const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;  in exynos_cpuclk_post_rate_change()
237 	if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {  in exynos_cpuclk_post_rate_change()
238 		while ((cfg_data->prate * 1000) != ndata->new_rate) {  in exynos_cpuclk_post_rate_change()
239 			if (cfg_data->prate == 0)  in exynos_cpuclk_post_rate_change()
240 				return -EINVAL;  in exynos_cpuclk_post_rate_change()
245 	spin_lock_irqsave(cpuclk->lock, flags);  in exynos_cpuclk_post_rate_change()
252 	if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {  in exynos_cpuclk_post_rate_change()
253 		div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);  in exynos_cpuclk_post_rate_change()
258 	spin_unlock_irqrestore(cpuclk->lock, flags);  in exynos_cpuclk_post_rate_change()
278 /* handler for pre-rate change notification from parent clock */
282 	const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;  in exynos5433_cpuclk_pre_rate_change()
283 	unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);  in exynos5433_cpuclk_pre_rate_change()
289 	while ((cfg_data->prate * 1000) != ndata->new_rate) {  in exynos5433_cpuclk_pre_rate_change()
290 		if (cfg_data->prate == 0)  in exynos5433_cpuclk_pre_rate_change()
291 			return -EINVAL;  in exynos5433_cpuclk_pre_rate_change()
295 	spin_lock_irqsave(cpuclk->lock, flags);  in exynos5433_cpuclk_pre_rate_change()
298 	 * For the selected PLL clock frequency, get the pre-defined divider  in exynos5433_cpuclk_pre_rate_change()
301 	div0 = cfg_data->div0;  in exynos5433_cpuclk_pre_rate_change()
302 	div1 = cfg_data->div1;  in exynos5433_cpuclk_pre_rate_change()
310 	 * (this can result in too high speed of armclk output clocks).  in exynos5433_cpuclk_pre_rate_change()
312 	if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {  in exynos5433_cpuclk_pre_rate_change()
313 		unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);  in exynos5433_cpuclk_pre_rate_change()
315 		alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;  in exynos5433_cpuclk_pre_rate_change()
334 	spin_unlock_irqrestore(cpuclk->lock, flags);  in exynos5433_cpuclk_pre_rate_change()
338 /* handler for post-rate change notification from parent clock */
346 	spin_lock_irqsave(cpuclk->lock, flags);  in exynos5433_cpuclk_post_rate_change()
354 	spin_unlock_irqrestore(cpuclk->lock, flags);  in exynos5433_cpuclk_post_rate_change()
359  * This notifier function is called for the pre-rate and post-rate change
371 	base = cpuclk->ctrl_base;  in exynos_cpuclk_notifier_cb()
382  * This notifier function is called for the pre-rate and post-rate change
394 	base = cpuclk->ctrl_base;  in exynos5433_cpuclk_notifier_cb()
418 		return -ENOMEM;  in exynos_register_cpu_clock()
426 	cpuclk->hw.init = &init;  in exynos_register_cpu_clock()
427 	cpuclk->ctrl_base = ctx->reg_base + offset;  in exynos_register_cpu_clock()
428 	cpuclk->lock = &ctx->lock;  in exynos_register_cpu_clock()
429 	cpuclk->flags = flags;  in exynos_register_cpu_clock()
431 		cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;  in exynos_register_cpu_clock()
433 		cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;  in exynos_register_cpu_clock()
435 	cpuclk->alt_parent = __clk_get_hw(__clk_lookup(alt_parent));  in exynos_register_cpu_clock()
436 	if (!cpuclk->alt_parent) {  in exynos_register_cpu_clock()
439 		ret = -EINVAL;  in exynos_register_cpu_clock()
447 		ret = -EINVAL;  in exynos_register_cpu_clock()
451 	ret = clk_notifier_register(parent_clk, &cpuclk->clk_nb);  in exynos_register_cpu_clock()
458 	cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);  in exynos_register_cpu_clock()
459 	if (!cpuclk->cfg) {  in exynos_register_cpu_clock()
460 		ret = -ENOMEM;  in exynos_register_cpu_clock()
464 	ret = clk_hw_register(NULL, &cpuclk->hw);  in exynos_register_cpu_clock()
470 	samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id);  in exynos_register_cpu_clock()
474 	kfree(cpuclk->cfg);  in exynos_register_cpu_clock()
476 	clk_notifier_unregister(parent_clk, &cpuclk->clk_nb);  in exynos_register_cpu_clock()