17 #include <linux/clk-provider.h>
23 #include "clk.h"
38 	if (socfpgaclk->fixed_div)  in socfpga_gate_clk_recalc_rate()
39 		div = socfpgaclk->fixed_div;  in socfpga_gate_clk_recalc_rate()
40 	else if (socfpgaclk->div_reg) {  in socfpga_gate_clk_recalc_rate()
41 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;  in socfpga_gate_clk_recalc_rate()
42 		val &= GENMASK(socfpgaclk->width - 1, 0);  in socfpga_gate_clk_recalc_rate()
56 	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {  in socfpga_clk_prepare()
58 			switch (socfpgaclk->clk_phase[i]) {  in socfpga_clk_prepare()
90 		if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))  in socfpga_clk_prepare()
91 			regmap_write(socfpgaclk->sys_mgr_base_addr,  in socfpga_clk_prepare()
112 	struct clk *clk;  in __socfpga_gate_init()  local
114 	const char *clk_name = node->name;  in __socfpga_gate_init()
123 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);  in __socfpga_gate_init()
128 		socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0];  in __socfpga_gate_init()
129 		socfpga_clk->hw.bit_idx = clk_gate[1];  in __socfpga_gate_init()
135 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);  in __socfpga_gate_init()
137 		socfpga_clk->fixed_div = 0;  in __socfpga_gate_init()
139 		socfpga_clk->fixed_div = fixed_div;  in __socfpga_gate_init()
141 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);  in __socfpga_gate_init()
143 		socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];  in __socfpga_gate_init()
144 		socfpga_clk->shift = div_reg[1];  in __socfpga_gate_init()
145 		socfpga_clk->width = div_reg[2];  in __socfpga_gate_init()
147 		socfpga_clk->div_reg = NULL;  in __socfpga_gate_init()
150 	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);  in __socfpga_gate_init()
152 		socfpga_clk->clk_phase[0] = clk_phase[0];  in __socfpga_gate_init()
153 		socfpga_clk->clk_phase[1] = clk_phase[1];  in __socfpga_gate_init()
155 		socfpga_clk->sys_mgr_base_addr =  in __socfpga_gate_init()
156 			syscon_regmap_lookup_by_compatible("altr,sys-mgr");  in __socfpga_gate_init()
157 		if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {  in __socfpga_gate_init()
158 			pr_err("%s: failed to find altr,sys-mgr regmap!\n",  in __socfpga_gate_init()
164 	of_property_read_string(node, "clock-output-names", &clk_name);  in __socfpga_gate_init()
172 	socfpga_clk->hw.hw.init = &init;  in __socfpga_gate_init()
174 	clk = clk_register(NULL, &socfpga_clk->hw.hw);  in __socfpga_gate_init()
175 	if (WARN_ON(IS_ERR(clk))) {  in __socfpga_gate_init()
179 	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);  in __socfpga_gate_init()