2  *  Copyright 2011-2012 Calxeda, Inc.
3  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
15  * Based from clk-highbank.c
19 #include <linux/clk-provider.h>
25 #include "clk.h"
44 	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {  in socfpga_clk_get_parent()
48 	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {  in socfpga_clk_get_parent()
54 	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))  in socfpga_clk_get_parent()
56 	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||  in socfpga_clk_get_parent()
57 			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))  in socfpga_clk_get_parent()
69 	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {  in socfpga_clk_set_parent()
74 	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {  in socfpga_clk_set_parent()
81 		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {  in socfpga_clk_set_parent()
84 		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||  in socfpga_clk_set_parent()
85 			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {  in socfpga_clk_set_parent()
104 	if (socfpgaclk->fixed_div)  in socfpga_clk_recalc_rate()
105 		div = socfpgaclk->fixed_div;  in socfpga_clk_recalc_rate()
106 	else if (socfpgaclk->div_reg) {  in socfpga_clk_recalc_rate()
107 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;  in socfpga_clk_recalc_rate()
108 		val &= GENMASK(socfpgaclk->width - 1, 0);  in socfpga_clk_recalc_rate()
110 		if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)  in socfpga_clk_recalc_rate()
127 	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {  in socfpga_clk_prepare()
128 		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");  in socfpga_clk_prepare()
130 			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);  in socfpga_clk_prepare()
131 			return -EINVAL;  in socfpga_clk_prepare()
135 			switch (socfpgaclk->clk_phase[i]) {  in socfpga_clk_prepare()
186 	struct clk *clk;  in __socfpga_gate_init()  local
188 	const char *clk_name = node->name;  in __socfpga_gate_init()
197 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);  in __socfpga_gate_init()
202 		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];  in __socfpga_gate_init()
203 		socfpga_clk->hw.bit_idx = clk_gate[1];  in __socfpga_gate_init()
209 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);  in __socfpga_gate_init()
211 		socfpga_clk->fixed_div = 0;  in __socfpga_gate_init()
213 		socfpga_clk->fixed_div = fixed_div;  in __socfpga_gate_init()
215 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);  in __socfpga_gate_init()
217 		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];  in __socfpga_gate_init()
218 		socfpga_clk->shift = div_reg[1];  in __socfpga_gate_init()
219 		socfpga_clk->width = div_reg[2];  in __socfpga_gate_init()
221 		socfpga_clk->div_reg = NULL;  in __socfpga_gate_init()
224 	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);  in __socfpga_gate_init()
226 		socfpga_clk->clk_phase[0] = clk_phase[0];  in __socfpga_gate_init()
227 		socfpga_clk->clk_phase[1] = clk_phase[1];  in __socfpga_gate_init()
230 	of_property_read_string(node, "clock-output-names", &clk_name);  in __socfpga_gate_init()
238 	socfpga_clk->hw.hw.init = &init;  in __socfpga_gate_init()
240 	clk = clk_register(NULL, &socfpga_clk->hw.hw);  in __socfpga_gate_init()
241 	if (WARN_ON(IS_ERR(clk))) {  in __socfpga_gate_init()
245 	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);  in __socfpga_gate_init()