30 #define PLL_BW_GOODREF   (0L)
83 	.nrst	= { CLKGEN_FIELD(0x2f0, 0x1, 0),
84 		    CLKGEN_FIELD(0x2f0, 0x1, 1),
85 		    CLKGEN_FIELD(0x2f0, 0x1, 2),
86 		    CLKGEN_FIELD(0x2f0, 0x1, 3) },
87 	.npda	= CLKGEN_FIELD(0x2f0, 0x1, 12),
88 	.nsb	= { CLKGEN_FIELD(0x2f0, 0x1, 8),
89 		    CLKGEN_FIELD(0x2f0, 0x1, 9),
90 		    CLKGEN_FIELD(0x2f0, 0x1, 10),
91 		    CLKGEN_FIELD(0x2f0, 0x1, 11) },
93 	.nsdiv	= { CLKGEN_FIELD(0x304, 0x1, 24),
94 		    CLKGEN_FIELD(0x308, 0x1, 24),
95 		    CLKGEN_FIELD(0x30c, 0x1, 24),
96 		    CLKGEN_FIELD(0x310, 0x1, 24) },
97 	.mdiv	= { CLKGEN_FIELD(0x304, 0x1f, 15),
98 		    CLKGEN_FIELD(0x308, 0x1f, 15),
99 		    CLKGEN_FIELD(0x30c, 0x1f, 15),
100 		    CLKGEN_FIELD(0x310, 0x1f, 15) },
101 	.en	= { CLKGEN_FIELD(0x2fc, 0x1, 0),
102 		    CLKGEN_FIELD(0x2fc, 0x1, 1),
103 		    CLKGEN_FIELD(0x2fc, 0x1, 2),
104 		    CLKGEN_FIELD(0x2fc, 0x1, 3) },
105 	.ndiv	= CLKGEN_FIELD(0x2f4, 0x7, 16),
106 	.pe	= { CLKGEN_FIELD(0x304, 0x7fff, 0),
107 		    CLKGEN_FIELD(0x308, 0x7fff, 0),
108 		    CLKGEN_FIELD(0x30c, 0x7fff, 0),
109 		    CLKGEN_FIELD(0x310, 0x7fff, 0) },
110 	.sdiv	= { CLKGEN_FIELD(0x304, 0xf, 20),
111 		    CLKGEN_FIELD(0x308, 0xf, 20),
112 		    CLKGEN_FIELD(0x30c, 0xf, 20),
113 		    CLKGEN_FIELD(0x310, 0xf, 20) },
115 	.lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
125 	.nrst	= { CLKGEN_FIELD(0x2a0, 0x1, 0),
126 		    CLKGEN_FIELD(0x2a0, 0x1, 1),
127 		    CLKGEN_FIELD(0x2a0, 0x1, 2),
128 		    CLKGEN_FIELD(0x2a0, 0x1, 3) },
129 	.ndiv	= CLKGEN_FIELD(0x2a4, 0x7, 16),
130 	.pe	= { CLKGEN_FIELD(0x2b4, 0x7fff, 0),
131 		    CLKGEN_FIELD(0x2b8, 0x7fff, 0),
132 		    CLKGEN_FIELD(0x2bc, 0x7fff, 0),
133 		    CLKGEN_FIELD(0x2c0, 0x7fff, 0) },
134 	.sdiv	= { CLKGEN_FIELD(0x2b4, 0xf, 20),
135 		    CLKGEN_FIELD(0x2b8, 0xf, 20),
136 		    CLKGEN_FIELD(0x2bc, 0xf, 20),
137 		    CLKGEN_FIELD(0x2c0, 0xf, 20) },
138 	.npda	= CLKGEN_FIELD(0x2a0, 0x1, 12),
139 	.nsb	= { CLKGEN_FIELD(0x2a0, 0x1, 8),
140 		    CLKGEN_FIELD(0x2a0, 0x1, 9),
141 		    CLKGEN_FIELD(0x2a0, 0x1, 10),
142 		    CLKGEN_FIELD(0x2a0, 0x1, 11) },
144 	.nsdiv	= { CLKGEN_FIELD(0x2b4, 0x1, 24),
145 		    CLKGEN_FIELD(0x2b8, 0x1, 24),
146 		    CLKGEN_FIELD(0x2bc, 0x1, 24),
147 		    CLKGEN_FIELD(0x2c0, 0x1, 24) },
148 	.mdiv	= { CLKGEN_FIELD(0x2b4, 0x1f, 15),
149 		    CLKGEN_FIELD(0x2b8, 0x1f, 15),
150 		    CLKGEN_FIELD(0x2bc, 0x1f, 15),
151 		    CLKGEN_FIELD(0x2c0, 0x1f, 15) },
152 	.en	= { CLKGEN_FIELD(0x2ac, 0x1, 0),
153 		    CLKGEN_FIELD(0x2ac, 0x1, 1),
154 		    CLKGEN_FIELD(0x2ac, 0x1, 2),
155 		    CLKGEN_FIELD(0x2ac, 0x1, 3) },
157 	.lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
198 	unsigned long flags = 0, timeout = jiffies + msecs_to_jiffies(10);  in quadfs_pll_enable()
233 	return 0;  in quadfs_pll_enable()
239 	unsigned long flags = 0;  in quadfs_pll_disable()
251 		CLKGEN_WRITE(pll, nreset, 0);  in quadfs_pll_disable()
272 	return 0;  in clk_fs660c32_vco_get_rate()
279 	unsigned long rate = 0;  in quadfs_pll_fs660c32_recalc_rate()
318 	return 0;  in clk_fs660c32_vco_get_params()
344 	long hwrate = 0;  in quadfs_pll_fs660c32_set_rate()
345 	unsigned long flags = 0;  in quadfs_pll_fs660c32_set_rate()
357 	pr_debug("%s: %s new rate %ld [ndiv=0x%x]\n",  in quadfs_pll_fs660c32_set_rate()
374 	return 0;  in quadfs_pll_fs660c32_set_rate()
483 	CLKGEN_WRITE(fs, en[fs->chan], 0);  in quadfs_fsynth_program_enable()
488 	unsigned long flags = 0;  in quadfs_fsynth_program_rate()
495 	CLKGEN_WRITE(fs, en[fs->chan], 0);  in quadfs_fsynth_program_rate()
514 	unsigned long flags = 0;  in quadfs_fsynth_enable()
526 		CLKGEN_WRITE(fs, nrst[fs->chan], 0);  in quadfs_fsynth_enable()
533 	return 0;  in quadfs_fsynth_enable()
539 	unsigned long flags = 0;  in quadfs_fsynth_disable()
557 	pr_debug("%s: %s enable bit = 0x%x\n",  in quadfs_fsynth_is_enabled()
577 	 *       0        3  in clk_fs660c32_dig_get_rate()
585 	return 0;  in clk_fs660c32_dig_get_rate()
622 	return 0;  in clk_fs660c32_get_pe()
628 	int si;	/* sdiv_reg (8 downto 0) */  in clk_fs660c32_dig_get_params()
632 	unsigned long deviation = ~0;  in clk_fs660c32_dig_get_params()
638 	for (si = 0; (si <= 8) && deviation; si++) {  in clk_fs660c32_dig_get_params()
641 		r1 = clk_fs660c32_get_pe(0, si, &deviation,  in clk_fs660c32_dig_get_params()
657 	if (deviation == ~0) /* No solution found */  in clk_fs660c32_dig_get_params()
660 	/* pe fine tuning if deviation not 0: +/- 2 around computed pe value */  in clk_fs660c32_dig_get_params()
669 			p2 = 0;  in clk_fs660c32_dig_get_params()
686 	return 0;  in clk_fs660c32_dig_get_params()
715 	return 0;  in quadfs_fsynt_get_hw_value_for_recalc()
725 	unsigned long rate = 0;  in quadfs_find_best_rate()
740 	unsigned long rate = 0;  in quadfs_recalc_rate()
748 		return 0;  in quadfs_recalc_rate()
767 	pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n",  in quadfs_round_rate()
803 	memset(&params, 0, sizeof(struct stm_fs));  in quadfs_set_rate()
811 	return 0;  in quadfs_set_rate()
885 	for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) {  in st_of_create_quadfs_fsynths()
888 		unsigned long flags = 0;  in st_of_create_quadfs_fsynths()
898 		if (*clk_name == '\0')  in st_of_create_quadfs_fsynths()
931 	reg = of_iomap(np, 0);  in st_of_quadfs_setup()
935 	clk_parent_name = of_clk_get_parent_name(np, 0);  in st_of_quadfs_setup()