Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:ts
16 #include <linux/clk-provider.h>
33 #include "ccu-sun4i-a10.h"
43 .hw.init = CLK_HW_INIT("pll-core",
55 * With sigma-delta modulation for fractional-N on the audio PLL,
78 .hw.init = CLK_HW_INIT("pll-audio-base",
96 .hw.init = CLK_HW_INIT("pll-video0",
111 .hw.init = CLK_HW_INIT("pll-ve",
124 .hw.init = CLK_HW_INIT("pll-ve",
137 .hw.init = CLK_HW_INIT("pll-ddr-base",
144 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
151 .hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
163 .hw.init = CLK_HW_INIT("pll-periph-base",
170 static CLK_FIXED_FACTOR(pll_periph_clk, "pll-periph", "pll-periph-base",
173 /* Not documented on A10 */
181 .hw.init = CLK_HW_INIT("pll-periph-sata",
182 "pll-periph-base",
197 .hw.init = CLK_HW_INIT("pll-video1",
204 /* Not present on A10 */
211 .hw.init = CLK_HW_INIT("pll-gpu",
221 "pll-core", "pll-periph" };
254 static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
255 "pll-periph" };
288 static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
296 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
299 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
301 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
303 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
305 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
307 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
309 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
311 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
313 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
315 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
317 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
319 static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
321 static SUNXI_CCU_GATE(ahb_mmc3_clk, "ahb-mmc3", "ahb",
323 static SUNXI_CCU_GATE(ahb_ms_clk, "ahb-ms", "ahb",
325 static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
327 static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
330 static SUNXI_CCU_GATE(ahb_ace_clk, "ahb-ace", "ahb",
332 static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
334 static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
336 static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
338 static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
340 static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
342 static SUNXI_CCU_GATE(ahb_spi3_clk, "ahb-spi3", "ahb",
344 static SUNXI_CCU_GATE(ahb_pata_clk, "ahb-pata", "ahb",
347 static SUNXI_CCU_GATE(ahb_sata_clk, "ahb-sata", "ahb",
350 static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
352 /* Not present on A10 */
353 static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
356 static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
358 static SUNXI_CCU_GATE(ahb_tvd_clk, "ahb-tvd", "ahb",
360 static SUNXI_CCU_GATE(ahb_tve0_clk, "ahb-tve0", "ahb",
362 static SUNXI_CCU_GATE(ahb_tve1_clk, "ahb-tve1", "ahb",
364 static SUNXI_CCU_GATE(ahb_lcd0_clk, "ahb-lcd0", "ahb",
366 static SUNXI_CCU_GATE(ahb_lcd1_clk, "ahb-lcd1", "ahb",
368 static SUNXI_CCU_GATE(ahb_csi0_clk, "ahb-csi0", "ahb",
370 static SUNXI_CCU_GATE(ahb_csi1_clk, "ahb-csi1", "ahb",
372 /* Not present on A10 */
373 static SUNXI_CCU_GATE(ahb_hdmi1_clk, "ahb-hdmi1", "ahb",
375 static SUNXI_CCU_GATE(ahb_hdmi0_clk, "ahb-hdmi0", "ahb",
377 static SUNXI_CCU_GATE(ahb_de_be0_clk, "ahb-de-be0", "ahb",
379 static SUNXI_CCU_GATE(ahb_de_be1_clk, "ahb-de-be1", "ahb",
381 static SUNXI_CCU_GATE(ahb_de_fe0_clk, "ahb-de-fe0", "ahb",
383 static SUNXI_CCU_GATE(ahb_de_fe1_clk, "ahb-de-fe1", "ahb",
385 /* Not present on A10 */
386 static SUNXI_CCU_GATE(ahb_gmac_clk, "ahb-gmac", "ahb",
388 static SUNXI_CCU_GATE(ahb_mp_clk, "ahb-mp", "ahb",
390 static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
393 static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
395 static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
397 static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",
399 static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",
401 /* Not present on A10 */
402 static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",
404 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
406 static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",
408 static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",
410 /* Not present on A10 */
411 static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",
413 static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
416 static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
418 static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
420 static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
422 /* Not present on A10 */
423 static SUNXI_CCU_GATE(apb1_i2c3_clk, "apb1-i2c3", "apb1",
425 static SUNXI_CCU_GATE(apb1_can_clk, "apb1-can", "apb1",
427 static SUNXI_CCU_GATE(apb1_scr_clk, "apb1-scr", "apb1",
429 static SUNXI_CCU_GATE(apb1_ps20_clk, "apb1-ps20", "apb1",
431 static SUNXI_CCU_GATE(apb1_ps21_clk, "apb1-ps21", "apb1",
433 /* Not present on A10 */
434 static SUNXI_CCU_GATE(apb1_i2c4_clk, "apb1-i2c4", "apb1",
436 static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
438 static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
440 static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
442 static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
444 static SUNXI_CCU_GATE(apb1_uart4_clk, "apb1-uart4", "apb1",
446 static SUNXI_CCU_GATE(apb1_uart5_clk, "apb1-uart5", "apb1",
448 static SUNXI_CCU_GATE(apb1_uart6_clk, "apb1-uart6", "apb1",
450 static SUNXI_CCU_GATE(apb1_uart7_clk, "apb1-uart7", "apb1",
453 static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
454 "pll-ddr-other" };
462 /* Undocumented on A10 */
477 /* MMC output and sample clocks are not present on A10 */
490 /* MMC output and sample clocks are not present on A10 */
503 /* MMC output and sample clocks are not present on A10 */
516 /* MMC output and sample clocks are not present on A10 */
522 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
557 /* Undocumented on A10 */
565 /* TODO: Check whether A10 actually supports osc32k as 4th parent? */
566 static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
567 "pll-ddr-other" };
581 static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
582 "pll-ddr-other", "osc32k" };
597 static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
598 "pll-audio-2x", "pll-audio" };
605 /* Undocumented on A10 */
628 * SATA-CLKM / SATA-CLKP pins.
630 static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
635 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "pll-periph",
637 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "pll-periph",
639 static SUNXI_CCU_GATE(usb_phy_clk, "usb-phy", "pll-periph",
651 /* Not present on A10 */
655 /* Not present on A10 */
659 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
661 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "pll-ddr",
663 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "pll-ddr",
665 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
667 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
669 static SUNXI_CCU_GATE(dram_tve0_clk, "dram-tve0", "pll-ddr",
671 static SUNXI_CCU_GATE(dram_tve1_clk, "dram-tve1", "pll-ddr",
674 /* Clock seems to be critical only on sun4i */
675 static SUNXI_CCU_GATE(dram_out_clk, "dram-out", "pll-ddr",
677 static SUNXI_CCU_GATE(dram_de_fe1_clk, "dram-de-fe1", "pll-ddr",
679 static SUNXI_CCU_GATE(dram_de_fe0_clk, "dram-de-fe0", "pll-ddr",
681 static SUNXI_CCU_GATE(dram_de_be0_clk, "dram-de-be0", "pll-ddr",
683 static SUNXI_CCU_GATE(dram_de_be1_clk, "dram-de-be1", "pll-ddr",
685 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "pll-ddr",
687 static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
690 static const char *const de_parents[] = { "pll-video0", "pll-video1",
691 "pll-ddr-other" };
692 static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
695 static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
698 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
701 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
704 /* Undocumented on A10 */
705 static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
708 static const char *const disp_parents[] = { "pll-video0", "pll-video1",
709 "pll-video0-2x", "pll-video1-2x" };
710 static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
712 static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
715 static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
716 "pll-ddr-other", "pll-periph" };
718 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
722 /* TVD clock setup for A10 */
723 static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
729 "tvd-sclk2", tvd_parents,
737 static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
740 static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
746 "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
750 static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
756 "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
760 static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
761 "pll-video0-2x", "pll-video1-2x"};
771 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
773 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
778 static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
786 static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
787 "pll-ddr-other",
788 "pll-video1" };
793 static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
794 "pll-ddr-other", "pll-video1",
795 "pll-gpu" };
802 static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
803 "pll-ddr-other" };
807 static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
808 "pll-ddr-other" };
813 static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
815 static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
840 .hw.init = CLK_HW_INIT_PARENTS("out-a",
859 .hw.init = CLK_HW_INIT_PARENTS("out-b",
1038 /* Post-divider for pll-audio is hardcoded to 1 */
1039 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
1040 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1041 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
1042 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
1043 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
1044 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1045 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
1046 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
1047 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
1048 "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
1049 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
1050 "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
1441 * settings interfere with sigma-delta modulation and result in sun4i_ccu_init()
1446 /* Force the PLL-Audio-1x divider to 1 */ in sun4i_ccu_init()
1457 * NB! These bits are undocumented in A10 manual. in sun4i_ccu_init()
1470 CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
1477 CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",