Lines Matching +full:4 +full:- +full:bit
2 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
14 #include <linux/clk-provider.h>
28 #include "ccu-sun9i-a80.h"
33 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
35 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
43 .enable = BIT(31),
44 .lock = BIT(0),
50 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
57 .enable = BIT(31),
58 .lock = BIT(1),
64 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
78 .enable = BIT(31),
79 .lock = BIT(2),
86 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
93 .enable = BIT(31),
94 .lock = BIT(3),
102 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
109 .enable = BIT(31),
110 .lock = BIT(4),
118 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
125 .enable = BIT(31),
126 .lock = BIT(5),
134 .hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
141 .enable = BIT(31),
142 .lock = BIT(6),
149 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
156 .enable = BIT(31),
157 .lock = BIT(7),
165 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
172 .enable = BIT(31),
173 .lock = BIT(8),
181 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
188 .enable = BIT(31),
189 .lock = BIT(9),
197 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
204 .enable = BIT(31),
205 .lock = BIT(10),
213 .hw.init = CLK_HW_INIT("pll-isp", "osc24M",
220 .enable = BIT(31),
221 .lock = BIT(11),
229 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
235 static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
239 static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
247 { .val = 3, .div = 4 },
248 { .val = 4, .div = 4 },
249 { .val = 5, .div = 4 },
250 { .val = 6, .div = 4 },
251 { .val = 7, .div = 4 },
265 static const char * const gtbus_parents[] = { "osc24M", "pll-periph0",
266 "pll-periph1", "pll-periph1" };
270 static const char * const ahb_parents[] = { "gtbus", "pll-periph0",
271 "pll-periph1", "pll-periph1" };
308 static const char * const apb_parents[] = { "osc24M", "pll-periph0" };
347 0x080, 0, 3, 24, 2, BIT(31), 0);
350 0x084, 0, 3, 24, 2, BIT(31), 0);
358 .enable = BIT(31),
363 .width = 4,
370 .hw.init = CLK_HW_INIT_PARENTS("out-a",
378 .enable = BIT(31),
383 .width = 4,
390 .hw.init = CLK_HW_INIT_PARENTS("out-b",
397 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0" };
399 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents,
401 0, 4, /* M */
403 24, 4, /* mux */
404 BIT(31), /* gate */
407 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_1_clk, "nand0-1", mod0_default_parents,
409 0, 4, /* M */
411 24, 4, /* mux */
412 BIT(31), /* gate */
415 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents,
417 0, 4, /* M */
419 24, 4, /* mux */
420 BIT(31), /* gate */
423 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_1_clk, "nand1-1", mod0_default_parents,
425 0, 4, /* M */
427 24, 4, /* mux */
428 BIT(31), /* gate */
433 0, 4, /* M */
435 24, 4, /* mux */
436 BIT(31), /* gate */
439 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
441 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
446 0, 4, /* M */
448 24, 4, /* mux */
449 BIT(31), /* gate */
452 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
454 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
459 0, 4, /* M */
461 24, 4, /* mux */
462 BIT(31), /* gate */
465 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
467 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
472 0, 4, /* M */
474 24, 4, /* mux */
475 BIT(31), /* gate */
478 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3-sample", "mmc3",
480 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3-output", "mmc3",
485 0, 4, /* M */
487 24, 4, /* mux */
488 BIT(31), /* gate */
491 static const char * const ss_parents[] = { "osc24M", "pll-periph",
492 "pll-periph1" };
495 .enable = BIT(31),
496 .m = _SUNXI_CCU_DIV(0, 4),
498 .mux = _SUNXI_CCU_MUX_TABLE(24, 4, ss_table),
510 0, 4, /* M */
512 24, 4, /* mux */
513 BIT(31), /* gate */
518 0, 4, /* M */
520 24, 4, /* mux */
521 BIT(31), /* gate */
526 0, 4, /* M */
528 24, 4, /* mux */
529 BIT(31), /* gate */
534 0, 4, /* M */
536 24, 4, /* mux */
537 BIT(31), /* gate */
540 static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
541 0x440, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
542 static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
543 0x444, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
544 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
545 0x44c, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
547 static const char * const sdram_parents[] = { "pll-periph0", "pll-ddr" };
553 8, 4, /* M */
554 12, 4, /* mux */
558 static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490,
559 0, 4, BIT(31), CLK_SET_RATE_PARENT);
561 static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0);
563 static const char * const mp_parents[] = { "pll-video1", "pll-gpu", "pll-de" };
567 0, 4, /* M */
568 24, 4, /* mux */
569 BIT(31), /* gate */
572 static const char * const display_parents[] = { "pll-video0", "pll-video1" };
578 0, 4, /* M */
579 24, 4, /* mux */
580 BIT(31), /* gate */
587 0, 4, /* M */
588 24, 4, /* mux */
589 BIT(31), /* gate */
593 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
596 0, 4, /* M */
597 24, 4, /* mux */
598 BIT(31), /* gate */
601 static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video1" };
603 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
606 0, 4, /* M */
607 24, 4, /* mux */
608 BIT(31), /* gate */
614 0, 4, /* M */
615 24, 4, /* mux */
616 BIT(31), /* gate */
620 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0);
622 static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc,
623 0, 4, BIT(31), 0);
625 static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0,
626 0, 4, BIT(31), CLK_SET_RATE_PARENT);
628 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0);
630 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi0-mclk",
633 0, 4, /* M */
634 24, 4, /* mux */
635 BIT(31), /* gate */
638 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi1-mclk",
641 0, 4, /* M */
642 24, 4, /* mux */
643 BIT(31), /* gate */
646 static const char * const fd_parents[] = { "pll-periph0", "pll-isp" };
650 0, 4, /* M */
651 24, 4, /* mux */
652 BIT(31), /* gate */
654 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0,
655 16, 3, BIT(31), CLK_SET_RATE_PARENT);
657 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x4d4, BIT(31), 0);
659 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0,
660 0, 3, BIT(31), CLK_SET_RATE_PARENT);
661 static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4,
662 0, 3, BIT(31), CLK_SET_RATE_PARENT);
664 static const char * const gpu_axi_parents[] = { "pll-periph0", "pll-gpu" };
666 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_axi_clk, "gpu-axi",
669 0, 4, /* M */
670 24, 4, /* mux */
671 BIT(31), /* gate */
674 static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500,
675 0, 4, BIT(31), 0);
677 static SUNXI_CCU_M_WITH_GATE(ac97_clk, "ac97", "pll-audio",
678 0x504, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
680 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_hsi_clk, "mipi-hsi",
682 0, 4, /* M */
683 24, 4, /* mux */
684 BIT(31), /* gate */
687 static const char * const gpadc_parents[] = { "osc24M", "pll-audio", "osc32k" };
688 static const u8 gpadc_table[] = { 0, 4, 7 };
690 .enable = BIT(31),
691 .m = _SUNXI_CCU_DIV(0, 4),
693 .mux = _SUNXI_CCU_MUX_TABLE(24, 4, gpadc_table),
706 .enable = BIT(31),
707 .m = _SUNXI_CCU_DIV(0, 4),
709 .mux = _SUNXI_CCU_MUX_TABLE(24, 4, cir_tx_table),
712 .hw.init = CLK_HW_INIT_PARENTS("cir-tx",
720 static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0",
721 0x580, BIT(0), 0);
722 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0",
723 0x580, BIT(1), 0);
724 static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0",
725 0x580, BIT(3), 0);
726 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0",
727 0x580, BIT(5), 0);
728 static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0",
729 0x580, BIT(8), 0);
730 static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0",
731 0x580, BIT(12), 0);
732 static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0",
733 0x580, BIT(13), 0);
734 static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0",
735 0x580, BIT(14), 0);
736 static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0",
737 0x580, BIT(15), 0);
738 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0",
739 0x580, BIT(16), 0);
740 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0",
741 0x580, BIT(18), 0);
742 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0",
743 0x580, BIT(20), 0);
744 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0",
745 0x580, BIT(21), 0);
746 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0",
747 0x580, BIT(22), 0);
748 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0",
749 0x580, BIT(23), 0);
752 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
753 0x584, BIT(0), 0);
754 static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1",
755 0x584, BIT(1), 0);
756 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
757 0x584, BIT(17), 0);
758 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
759 0x584, BIT(21), 0);
760 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
761 0x584, BIT(22), 0);
762 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
763 0x584, BIT(23), 0);
764 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
765 0x584, BIT(24), 0);
768 static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2",
769 0x588, BIT(0), 0);
770 static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2",
771 0x588, BIT(1), 0);
772 static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2",
773 0x588, BIT(2), 0);
774 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2",
775 0x588, BIT(4), 0);
776 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2",
777 0x588, BIT(5), 0);
778 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2",
779 0x588, BIT(7), 0);
780 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2",
781 0x588, BIT(8), 0);
782 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2",
783 0x588, BIT(11), 0);
786 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0",
787 0x590, BIT(1), 0);
788 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0",
789 0x590, BIT(5), 0);
790 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0",
791 0x590, BIT(11), 0);
792 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0",
793 0x590, BIT(12), 0);
794 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0",
795 0x590, BIT(13), 0);
796 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0",
797 0x590, BIT(15), 0);
798 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0",
799 0x590, BIT(17), 0);
800 static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0",
801 0x590, BIT(18), 0);
802 static SUNXI_CCU_GATE(bus_cir_tx_clk, "bus-cir-tx", "apb0",
803 0x590, BIT(19), 0);
806 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1",
807 0x594, BIT(0), 0);
808 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1",
809 0x594, BIT(1), 0);
810 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1",
811 0x594, BIT(2), 0);
812 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1",
813 0x594, BIT(3), 0);
814 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb1",
815 0x594, BIT(4), 0);
816 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1",
817 0x594, BIT(16), 0);
818 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1",
819 0x594, BIT(17), 0);
820 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1",
821 0x594, BIT(18), 0);
822 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1",
823 0x594, BIT(19), 0);
824 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1",
825 0x594, BIT(20), 0);
826 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1",
827 0x594, BIT(21), 0);
1120 [RST_BUS_FD] = { 0x5a0, BIT(0) },
1121 [RST_BUS_VE] = { 0x5a0, BIT(1) },
1122 [RST_BUS_GPU_CTRL] = { 0x5a0, BIT(3) },
1123 [RST_BUS_SS] = { 0x5a0, BIT(5) },
1124 [RST_BUS_MMC] = { 0x5a0, BIT(8) },
1125 [RST_BUS_NAND0] = { 0x5a0, BIT(12) },
1126 [RST_BUS_NAND1] = { 0x5a0, BIT(13) },
1127 [RST_BUS_SDRAM] = { 0x5a0, BIT(14) },
1128 [RST_BUS_SATA] = { 0x5a0, BIT(16) },
1129 [RST_BUS_TS] = { 0x5a0, BIT(18) },
1130 [RST_BUS_SPI0] = { 0x5a0, BIT(20) },
1131 [RST_BUS_SPI1] = { 0x5a0, BIT(21) },
1132 [RST_BUS_SPI2] = { 0x5a0, BIT(22) },
1133 [RST_BUS_SPI3] = { 0x5a0, BIT(23) },
1136 [RST_BUS_OTG] = { 0x5a4, BIT(0) },
1137 [RST_BUS_OTG_PHY] = { 0x5a4, BIT(1) },
1138 [RST_BUS_MIPI_HSI] = { 0x5a4, BIT(9) },
1139 [RST_BUS_GMAC] = { 0x5a4, BIT(17) },
1140 [RST_BUS_MSGBOX] = { 0x5a4, BIT(21) },
1141 [RST_BUS_SPINLOCK] = { 0x5a4, BIT(22) },
1142 [RST_BUS_HSTIMER] = { 0x5a4, BIT(23) },
1143 [RST_BUS_DMA] = { 0x5a4, BIT(24) },
1146 [RST_BUS_LCD0] = { 0x5a8, BIT(0) },
1147 [RST_BUS_LCD1] = { 0x5a8, BIT(1) },
1148 [RST_BUS_EDP] = { 0x5a8, BIT(2) },
1149 [RST_BUS_LVDS] = { 0x5a8, BIT(3) },
1150 [RST_BUS_CSI] = { 0x5a8, BIT(4) },
1151 [RST_BUS_HDMI0] = { 0x5a8, BIT(5) },
1152 [RST_BUS_HDMI1] = { 0x5a8, BIT(6) },
1153 [RST_BUS_DE] = { 0x5a8, BIT(7) },
1154 [RST_BUS_MP] = { 0x5a8, BIT(8) },
1155 [RST_BUS_GPU] = { 0x5a8, BIT(9) },
1156 [RST_BUS_MIPI_DSI] = { 0x5a8, BIT(11) },
1159 [RST_BUS_SPDIF] = { 0x5b0, BIT(1) },
1160 [RST_BUS_AC97] = { 0x5b0, BIT(11) },
1161 [RST_BUS_I2S0] = { 0x5b0, BIT(12) },
1162 [RST_BUS_I2S1] = { 0x5b0, BIT(13) },
1163 [RST_BUS_LRADC] = { 0x5b0, BIT(15) },
1164 [RST_BUS_GPADC] = { 0x5b0, BIT(17) },
1165 [RST_BUS_CIR_TX] = { 0x5b0, BIT(19) },
1168 [RST_BUS_I2C0] = { 0x5b4, BIT(0) },
1169 [RST_BUS_I2C1] = { 0x5b4, BIT(1) },
1170 [RST_BUS_I2C2] = { 0x5b4, BIT(2) },
1171 [RST_BUS_I2C3] = { 0x5b4, BIT(3) },
1172 [RST_BUS_I2C4] = { 0x5b4, BIT(4) },
1173 [RST_BUS_UART0] = { 0x5b4, BIT(16) },
1174 [RST_BUS_UART1] = { 0x5b4, BIT(17) },
1175 [RST_BUS_UART2] = { 0x5b4, BIT(18) },
1176 [RST_BUS_UART3] = { 0x5b4, BIT(19) },
1177 [RST_BUS_UART4] = { 0x5b4, BIT(20) },
1178 [RST_BUS_UART5] = { 0x5b4, BIT(21) },
1200 if (!(val & BIT(SUN9I_A80_PLL_P_SHIFT))) in sun9i_a80_cpu_pll_fixup()
1211 val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1, in sun9i_a80_cpu_pll_fixup()
1216 val &= ~BIT(SUN9I_A80_PLL_P_SHIFT); in sun9i_a80_cpu_pll_fixup()
1228 reg = devm_ioremap_resource(&pdev->dev, res); in sun9i_a80_ccu_probe()
1234 val &= ~(BIT(16) | BIT(18)); in sun9i_a80_ccu_probe()
1241 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun9i_a80_ccu_desc); in sun9i_a80_ccu_probe()
1245 { .compatible = "allwinner,sun9i-a80-ccu" },
1252 .name = "sun9i-a80-ccu",